Method for manufacturing a gate-control diode semiconductor memory device

• US 8,426,271 B1
• Filed: 06/27/2012
• Issued: 04/23/2013
• Est. Priority Date: 01/05/2012
• Status: Active Grant

• Current Assignee: Fudan University
• Original Assignee: Fudan University
• Inventors: Wang, Pengfei, Cao, Chengwei, Sun, Qingqing, Zhang, Wei
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US13/534,998
• Time in Patent Office: 300 Days
• Field of Search: 438/104, 438/257, 438/261, 438/263, 438/264, 438/238, 438/239, 438/240, 257/43
• US Class Current: 438/257
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence

Abstract

This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and the device is of a simple gate-control pn junction structure; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The quantity of charges in the floating gate determines the device threshold voltage, thus realizing the memory functions. This invention features capacity of manufacturing memory devices able to reduce the chip power consumption through advantages of high driving current and small sub threshold swing, is applicable to semiconductor memory devices manufacturing based on flexible substrates and flat panel displays and floating gate memories, etc.

Claims

1. A method for manufacturing a gate-control diode semiconductor memory device, characterized in that, including the following steps:

provide a heavily-doped n-type silicon substrate;

form a first kind of insulation film on the n-type silicon substrate;

form a ZnO layer on the first kind of insulation film;

etch the ZnO layer to form an active region;

form a second kind of insulation film on the ZnO dielectric layer;

etch the second kind of insulation film to form a window located at one end of the ZnO active region;

coat the second kind of insulation film through spin coating with a layer of spin-coating dielectric of the first doping type which makes contact with the ZnO at the window of the second kind of insulation film;

form a doping region (namely a source region) of the first doping type at the window of the second kind of insulation film in the ZnO dielectric layer through the high-temperature diffusion process, wherein the other parts of the ZnO are not doped due to the barrier of the second kind of insulation film;

remove the residual spin-coating dielectric of the first doping type;

define a pattern through photoetching and etch the second kind of insulation film to define the position of a drain region and a channel region, wherein the drain region is on the opposite side of the source region on the ZnO and the channel region is between the source region and the drain region;

form a third kind of insulation film through deposition;

deposit a first layer of conductive material as the floating gate conductive material and define the pattern of the floating gate region thereof though photoetching and etching, wherein the floating gate region located between the source region on the ZnO active region and the drain region at the edge of the other end of the ZnO, is of square pattern, indirectly adjacent to the source region with a spacing of 10 nm-100 μ

m, and is 10 nm-100 μ

m away from the edge of the ZnO;

cover the exposed parts of the floating gate and the active region to form a fourth kind of insulation film;

etch out the fourth kind of insulation film on the source region and the drain region to define the positions of the contact holes of the drain and the source;

form a second kind of conductive film through deposition and etch the second kind of conductive film to form a drain electrode, a gate electrode and a source electrode which are independent of one another, wherein the source electrode makes contact with the source region on one side of the floating gate region through the source contact hole, the drain electrode makes contact with the ZnO drain region on the other side of the floating gate region through the drain contact hole and the gate electrode cover the non-etched fourth kind of insulation film on the floating gate region.

2. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the first kind of insulation film is of silicon oxide and with a thickness of 1-500 nm.

3. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the second kind of insulation film is of silicon oxide or silicon nitride.

4. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the third and fourth kinds of insulation film are of SiO₂, Si₃N₄ or high dieletric constant material HfO₂.

5. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the thickness of the ZnO dielectric layer is 1-100 nm.

6. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the first and second kinds of conductive film are of heavily-doped polycrystalline silicon, copper, tungsten, aluminum, titanium nitride or tantalum nitride.

7. The method for manufacturing a gate-control diode semiconductor memory device according to claim 1, characterized in that the first doping type is silicon p-type doping.