Methods of forming field effect transistors on substrates

• US 8,426,273 B2
• Filed: 12/15/2010
• Issued: 04/23/2013
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hanson, Robert J., Tang, Sanh D.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US12/969,418
• Publication Number:
  US 20110086476A1
• Time in Patent Office: 860 Days
• Field of Search: 438/268, 438/270, 438/197, 438/199, 438/589, 257/E21.428
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Claims

1. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

ion implanting conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions, the highest dopant concentration portions comprising 1×

10¹³ to 1×

10¹⁶ ions/cm³;

conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions, the semiconductive material having an exposed uppermost surface during the implanting and the anneal;

after the dopant activation anneal, etching an opening through the conductivity enhancing dopant into the semiconductive material of the substrate;

forming a gate dielectric that lines the entire sidewalls of the opening and directly overlies the uppermost surface of the semiconductive material; and

depositing material from which a conductive portion of the transistor gate is made into the opening.

2. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises elemental-form metal.

3. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises a conductive metal compound.

4. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises conductively doped semiconductive material.

5. The method of claim 1 further comprising prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion proximate each highest dopant concentration portion.

6. The method of claim 5 wherein said lower dopant concentration portions are formed lower in the semiconductive material than are the highest dopant concentration portions.

7. The method of claim 5 wherein said lower dopant concentration portions are of the same conductivity type as the highest dopant concentration portions.

8. The method of claim 7 wherein the dopant of the lower dopant concentration portions and the dopant of the highest dopant concentration portions are of the same composition.

9. The method of claim 5 wherein said lower dopant concentration portions are of different conductivity type as compared to the highest dopant concentration portions.

10. The method of claim 1 wherein the pair of source/drain regions is formed within bulk monocrystalline semiconductive material of the substrate.

11. The method of claim 10 wherein the field effect transistor gate is formed outwardly of the bulk monocrystalline semiconductive material.

12. The method of claim 10 wherein the field effect transistor gate is formed within an opening formed within the bulk monocrystalline semiconductive material.

13. The method of claim 1 wherein the pair of source/drain regions comprises elevated source/drain regions of a horizontally oriented field effect transistor.

14. The method of claim 13 wherein the substrate comprises bulk monocrystalline semiconductive material, the elevated source/drain regions being formed on the bulk monocrystalline semiconductive material.

15. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

ion implanting conductivity enhancing impurity dopant into an implant region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions, the highest dopant concentration portions comprising 1×

10¹³ to 1×

10¹⁶ ions/cm³;

after the ion implanting, conducting a dopant activation anneal of the implant region, an uppermost surface of the semiconductive material being exposed during the implanting and the anneal;

after the dopant activation anneal, etching an opening through the implant region into semiconductive material of the substrate;

forming gate dielectric material lining the entire sidewalls of the opening and directly on the uppermost surface of the semiconductive material; and

forming conductive material of the transistor gate within the opening.

16. The method of claim 15 wherein the opening is laterally centered relative to the implant region in at least one straight line cross section of the substrate.

17. The method of claim 15 further comprising prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion below the implant region, the opening being etched through the portion.

18. The method of claim 15 wherein the forming of conductive material comprises depositing conductive material to overfill the opening.

19. The method of claim 18 further comprising removing some of the deposited conductive material effective to recess it within the opening.

20. A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

ion implanting p-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the p-channel field effect transistor, the highest dopant concentration portions comprising 1×

10¹³ to 1×

10¹⁶ ions/cm³;

ion implanting n-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the n-channel field effect transistor;

simultaneously conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions of each of the n-channel field effect transistor and of the p-channel field effect transistor, an uppermost surface of the semiconductive material being exposed during the implanting and the anneal; and

after the dopant activation anneal, etching openings through the source/drain regions into the semiconductor material of the substrate;

forming gate oxide material lining an entirety of sidewalls of the openings and directly on the uppermost surface; and

depositing material from which conductive portions of the transistor gates are made into the openings.

21. The method of claim 20 comprising depositing different conductive gate materials for the respective p-channel and n-channel field effect transistors.

22. The method of claim 20 comprising depositing the same conductive gate material for the respective p-channel and n-channel field effect transistors.

23. A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

ion implanting p-type conductivity enhancing impurity dopant into a first region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the p-channel field effect transistor, the highest dopant concentration portions comprising 1×

10¹³ to 1×

10¹⁶ ions/cm³;

ion implanting n-type conductivity enhancing impurity dopant into a second region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the n-channel field effect transistor;

simultaneously conducting a dopant activation anneal of the first and second regions, an uppermost surface of the semiconductive material being exposed during the implanting and the anneal;

after the dopant activation anneal, etching a first opening through the first region into semiconductive material of the substrate and etching a second opening through the second region into semiconductive material of the substrate;

forming gate dielectric lining entire sidewalls within the first and second openings and on the uppermost surface of the semiconductive material; and

forming conductive material of the transistor gate of the p-channel field effect transistor over the gate dielectric within the first opening and conductive material of the transistor gate of the n-channel field effect transistor over the gate dielectric within the second opening.

24. The method of claim 23 further comprising prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion below each of the first and second regions, the first opening being etched through said lower dopant concentration portion received beneath first region, the second opening being etched through said lower dopant concentration portion received beneath second region.

25. The method of claim 23 wherein the semiconductive material of the first region, the semiconductive material of the second region, the semiconductive material into which the first opening is etched and the semiconductive material into which the second opening is etched comprise bulk monocrystalline semiconductive material.