Fabrication method of trenched power MOSFET

• US 8,426,275 B2
• Filed: 09/06/2011
• Issued: 04/23/2013
• Est. Priority Date: 01/09/2009
• Status: Active Grant

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Hsu, Hsiu-Wen, Tsai, Yi-Yun, Chang, Yuan-Shun, Tu, Kou-Way
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US13/225,555
• Publication Number:
  US 20110318895A1
• Time in Patent Office: 595 Days
• Field of Search: 257/E29.133
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.

Claims

1. A fabrication method of a trenched power MOSFET, at least comprising steps of:

forming a pattern layer having a first opening on a substrate;

removing a portion of the substrate by using the pattern layer as a mask, so as to form a gate trench in the substrate;

expanding a width of the gate trench;

after the step of expanding the width of the gate trench, forming a gate oxide layer on an inner surface of the gate trench;

after the step of forming the gate oxide layer, removing a portion of the gate oxide layer on a bottom of the gate trench by using the pattern layer as a mask, so as to form a second opening exposing the substrate and located in the gate oxide layer, wherein a width of the expanded gate trench is greater than a width of the second opening;

forming a thick oxide layer in the second opening;

forming two first heavily doped regions at two sides of the thick oxide layer;

forming a gate polysilicon structure in the gate trench;

forming a body layer to surround the gate trench; and

forming two source doped regions at two sides of the gate trench.

2. The fabrication method of claim 1, wherein the gate trench prior to the expanding step, the first opening and the second opening have substantially the same width.

3. The fabrication method of claim 1, wherein when the pattern layer is used as a mask, the width of the expanded gate trench is greater than a width of the first opening.

4. The fabrication method of claim 1, wherein a method of expanding the width of the gate trench comprises:

oxidizing the substrate to form a first oxide layer in the gate trench, wherein the first oxide layer at least covers a sidewall of the gate trench and consumes a portion of the substrate; and

removing the first oxide layer.

5. The fabrication method of claim 4, wherein the step of removing the first oxide layer comprises performing an isotropic etching process.

6. The fabrication method of claim 1, wherein a depth of the body layer is increased in a direction away from the gate trench, and the first heavily doped regions adjust a depth profile of the body layer.

7. The fabrication method of claim 1, further comprising forming a dielectric structure on the gate polysilicon structure after the step of forming the first heavily doped regions.

8. The fabrication method of claim 1, further comprising forming a first spacer structure in the first opening of the pattern layer after the step of forming the pattern layer, wherein the gate trench is formed in the substrate by using the pattern layer and the first spacer structure as a mask.

9. The fabrication method of claim 8, wherein the width the second opening is equal to a width of a third opening defined to correspond to the first spacer structure in the first opening.

10. The fabrication method of claim 9, wherein the gate trench prior to the expanding step, the second opening and the third opening have substantially the same width.

11. The fabrication method of claim 9, wherein the width of the expanded gate trench is greater than the width of the third opening.

12. The fabrication method of claim 1, wherein the thick oxide layer is formed in the second opening by a wet oxidation process.

13. The fabrication method of claim 1, wherein the thick oxide layer is formed in the second opening by a deposition process.

14. The fabrication method of claim 1, wherein a narrow trench is formed below the second opening during the step of forming the second opening, and an opening width of the narrow trench corresponds to the width of the second opening.

15. The fabrication method of claim 14, wherein the step of forming the first heavily doped regions comprises:

forming a heavily doped region in the substrate below the gate trench before the step of forming the second opening, so that the narrow trench penetrates the heavily doped region and the first heavily doped regions are formed at two sides of the narrow trench.

16. The fabrication method of claim 1, wherein the step of forming the first heavily doped regions comprises:

forming a heavily doped region in the substrate below the gate trench before the step of forming the second opening, so that the thick oxide layer penetrates the heavily doped region and the first heavily doped regions are formed at two sides of the thick oxide layer.

17. The fabrication method of claim 4, wherein a thickness of the first oxide layer is greater than a thickness of the gate oxide layer.

18. The fabrication method of claim 1, wherein the step of forming the first heavily doped regions comprises:

performing an ion implantation process after the step of forming the thick oxide layer, so that the first heavily doped regions are formed at two sides of the thick oxide layer.

19. The fabrication method of claim 18, wherein the ion implantation process comprises a tilt ion implantation process.

20. The fabrication method of claim 1, further comprising, after the step of forming the second opening, performing an etching process to expand the width of the first opening of the pattern layer, so as to expose an entire opening of the gate trench.

21. The fabrication method of claim 8, further comprising removing the first spacer structure to expose an entire opening of the gate trench after the step of forming the second opening.

22. The fabrication method of claim 7, wherein the dielectric structure is disposed in the first opening.

23. The fabrication method of claim 22, further comprising, after the step of forming the dielectric structure, forming a second spacer structure at two sides of the dielectric structure, so as to define the source doped regions at two sides of the gate trench.

24. The fabrication method of claim 7, wherein the dielectric structure is disposed in the gate trench.

25. The fabrication method of claim 24, further comprising, after the step of forming the dielectric structure:

removing a portion of the substrate by using the dielectric structure as a mask, so that the dielectric structure protrudes from the substrate; and

forming a spacer structure at two sides of the dielectric structure, so as to define the source doped regions at two sides of the gate trench.

26. The fabrication method of claim 1, further comprising removing the pattern layer after the step of forming the first heavily doped regions and before the step of forming the body layer.