Method of manufacturing semiconductor device, solid-state imaging device, and solid-state imaging apparatus

• US 8,426,287 B2
• Filed: 11/12/2010
• Issued: 04/23/2013
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yanagita, Masashi
• Primary Examiner(s): Nhu, David
• Application Number:
  US12/945,255
• Publication Number:
  US 20110127592A1
• Time in Patent Office: 893 Days
• Field of Search: 438/514, 438/700, 438/197, 438/383, 438/289, 438/141, 438/390, 438/391, 438/392, 438/70, 438/75, 257/E21.027, 257/E21.042, 257/E21.053, 257/E21.058, 257/E21.189, 257/E21.231, 257/E21.248, 257/E21.325, 257/E21.352, 257/E21.371, 257/E21.435, 257/291
• US Class Current: 438/383
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 31/0352 characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate;

forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate;

forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask; and

forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the isolation region is formed after the gate electrode of the transistor is formed.

3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the ion implantation of the impurity of the second conductivity type is performed in a state where the isolation region is covered with the mask when the lightly doped drain region is formed.

4. A semiconductor device comprising:

an isolation region which is an impurity region of a first conductivity type;

a source region and a drain region of a transistor which are impurity regions of a second conductivity type;

a gate electrode of the transistor which is provided on an insulator layer on a surface of a semiconductor substrate formed with the isolation region and the source region and the drain region of the transistor; and

a lightly doped drain region of the second conductivity type which is provided near the surface of the semiconductor substrate in a region narrower than a width of the gate electrode of the transistor.

5. The semiconductor device according to claim 4, wherein a width of the lightly doped drain region is approximately equivalent to a width of the source region and the drain region of the transistor or narrower than the width of the source region and the drain region of the transistor.