Self-aligned contact for replacement gate devices
First Claim
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1. A method of forming a semiconductor structure comprising:
- forming a gate electrode and a planarization dielectric layer on a semiconductor substrate, wherein a top metallic surface of said gate electrode is coplanar with a top surface of said planarization dielectric layer;
recessing a top surface of said gate electrode relative to said top surface of said planarization dielectric layer;
forming an etch stop layer contiguously on said recessed top surface of said gate electrode and on said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate electrode and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion;
forming a contact-level dielectric layer over said etch stop layer;
forming a via hole extending at least through said contact-level dielectric layer, said first portion of said etch stop layer, and a portion of said planarization dielectric layer, wherein said via hole is vertically spaced from said gate electrode by said second portion of said etch stop layer;
wherein said gate electrode is a replacement gate electrode formed by;
forming a disposable gate structure on said semiconductor substrate; and
replacing said disposable gate structure with a gate dielectric and at least one conductive material, wherein said gate electrode is a remaining portion of said at least one conductive material after removing said at least one conductive material from above a top surface of said planarization dielectric layer.
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Abstract
A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
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Citations
12 Claims
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1. A method of forming a semiconductor structure comprising:
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forming a gate electrode and a planarization dielectric layer on a semiconductor substrate, wherein a top metallic surface of said gate electrode is coplanar with a top surface of said planarization dielectric layer; recessing a top surface of said gate electrode relative to said top surface of said planarization dielectric layer; forming an etch stop layer contiguously on said recessed top surface of said gate electrode and on said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate electrode and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion; forming a contact-level dielectric layer over said etch stop layer; forming a via hole extending at least through said contact-level dielectric layer, said first portion of said etch stop layer, and a portion of said planarization dielectric layer, wherein said via hole is vertically spaced from said gate electrode by said second portion of said etch stop layer; wherein said gate electrode is a replacement gate electrode formed by; forming a disposable gate structure on said semiconductor substrate; and replacing said disposable gate structure with a gate dielectric and at least one conductive material, wherein said gate electrode is a remaining portion of said at least one conductive material after removing said at least one conductive material from above a top surface of said planarization dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. The method of claim l, further comprising:
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forming a dielectric gate spacer on sidewalls of said disposable gate structure; and forming a contact via structure through said contact-level dielectric layer, said etch stop layer, and said planarization dielectric layer, wherein said contact via structure is spaced from said gate electrode by said etch stop layer and said dielectric gate spacer.
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10. The method of claim l, wherein said at least one conductive material includes at least a titanium nitride portion and an aluminum portion, and said method includes:
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employing a wet etch solution including ammonium hydroxide and hydrogen peroxide to etch said titanium nitride portion; and employing a solution including at least sulfuric acid and hydrogen peroxide or a dilute hydrofluoric acid-containing solution to etch said aluminum portion.
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11. The method of claim l, wherein said at least one conductive material includes at least a tantalum nitride portion or a titanium nitride portion, and said method includes employing a chemical downstream etch (CDE) to etch said tantalum nitride portion or said titanium nitride portion, wherein said CDE employs at least one of CHF3, CF4, and Cl2 and does not generate plasma directly on said gate stack.
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12. The method of claim l, further comprising:
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forming another gate electrode concurrently with formation of said gate electrode on said semiconductor substrate, wherein a top metallic surface of said other gate electrode is coplanar with said top surface of said planarization dielectric layer; and covering said other gate electrode with a patterned mask layer, wherein said patterned mask layer does not overlie said gate electrode, and wherein said other gate electrode is not recessed while said top surface of said gate electrode is recessed relative to said top surface of said planarization dielectric layer.
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Specification