Semiconductor device and method for manufacturing the same

• US 8,426,868 B2
• Filed: 10/23/2009
• Issued: 04/23/2013
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Sasaki, Toshinari
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/604,622
• Publication Number:
  US 20100109003A1
• Time in Patent Office: 1,278 Days
• Field of Search: 438141-156, 438/726, 438/776, 438/795, 257/E21.046, 257/476, 257/29.079, 257/226, 257/273
• US Class Current: 257/72
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a pair of buffer regions having n-type conductivity over the second oxide semiconductor layer;

a source electrode layer over one of the pair of buffer regions and a drain electrode layer over the other of the pair of buffer regions,

wherein each of the second oxide semiconductor layer and the pair of buffer regions contains indium, gallium, and zinc,

wherein a thickness of the first oxide semiconductor layer is smaller than a thickness of the second oxide semiconductor layer, and

wherein an electrical conductivity of the first oxide semiconductor layer is higher than an electrical conductivity of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein a carrier concentration of the second oxide semiconductor layer is lower than 1×

10¹⁷/cm³.

3. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer contains indium, gallium, and zinc.

4. The semiconductor device according to claim 1, wherein the electrical conductivity of the first oxide semiconductor layer is higher than 1.0×

10<sup>−

3</sup> S/cm³.

5. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has a region between the source and drain electrode layers, and wherein the region between the source and drain electrode layers has a thickness smaller than that of a region overlapping with the source and drain electrode layers.

6. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a poster, an advertisement, an electronic book, a television set, a digital photo frame, a game machine and a phone.

7. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a pair of buffer regions having n-type conductivity over the second oxide semiconductor layer; and

a source electrode layer over one of the pair of buffer regions and a drain electrode layer over the other of the pair of buffer regions,

wherein each of the second oxide semiconductor layer and the pair of buffer regions contains indium, gallium, and zinc,

wherein a carrier concentration of the pair of buffer regions is higher than a carrier concentration of the second oxide semiconductor layer,

wherein a thickness of the first oxide semiconductor layer is smaller than a thickness of the second oxide semiconductor layer,

wherein an electrical conductivity of the first oxide semiconductor layer is higher than an electrical conductivity of the second oxide semiconductor layer, and

wherein an electrical conductivity of the pair of buffer regions is higher than the electrical conductivity of the first oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein the carrier concentration of the pair of buffer regions is 1×

10¹⁸/cm³ or higher.

9. The semiconductor device according to claim 7, wherein the carrier concentration of the second oxide semiconductor layer is lower than 1×

10¹⁷/cm³.

10. The semiconductor device according to claim 7, wherein the first oxide semiconductor layer contains indium, gallium, and zinc.

11. The semiconductor device according to claim 7, wherein the electrical conductivity of the first oxide semiconductor layer is higher than 1.0×

10<sup>−

3</sup> S/cm³.

12. The semiconductor device according to claim 7, wherein the second oxide semiconductor layer has a region between the source and drain electrode layers, and wherein the region between the source and drain electrode layers has a thickness smaller than that of a region overlapping with the source and drain electrode layers.

13. The semiconductor device according to claim 7, wherein the semiconductor device is one selected from the group consisting of a poster, an advertisement, an electronic book, a television set, a digital photo frame, a game machine and a phone.