Semiconductor device and method of manufacturing semiconductor device

• US 8,426,912 B2
• Filed: 09/26/2008
• Issued: 04/23/2013
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Izumi, Naoki
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US12/285,012
• Publication Number:
  US 20090085109A1
• Time in Patent Office: 1,670 Days
• Field of Search: 257/334, 257/333
• US Class Current: 257/334
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer;

a trench dug from the surface of the semiconductor layer to penetrate the body region;

a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region;

a gate insulating film formed on the bottom surface and the side surface of the trench;

a gate electrode embedded in the trench through the gate insulating film and so formed that a bottom surface of the gate electrode is in contact with the bottom surface of the trench via the gate insulating film, and a top surface of the gate electrode is lower by one stage than the surface of the source region;

a peripheral wall film formed on a peripheral edge portion of the top surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench, to cover said peripheral edge portion and to expose remaining portion of the top surface of the gate electrode;

an element isolation portion formed on the surface of the semiconductor layer for isolating a first element forming region and a second element forming region from each other, wherein the body region is formed in the first element forming region; and

a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) formed in the second element forming region.

2. The semiconductor device according to claim 1, wherein

the planar gate MOSFET comprises:

a planar gate electrode formed on the surface of the semiconductor layer in the second element forming region; and

a sidewall surrounding the planar gate electrode to cover the side surface of the planar gate electrode.

3. The semiconductor device according to claim 2, wherein the peripheral wall film and the sidewall are made of a same material.

4. The semiconductor device according to claim 1, further comprising:

a deep well region of a second conductivity type formed in the surface layer portion of the semiconductor layer in the second element forming region;

a first well region of a first conductivity type formed in a surface layer portion of the deep well region; and

a second well region of a second conductivity type formed in the surface layer portion of the deep well region isolatedly from the first well region.

5. The semiconductor device according to claim 4, wherein the deep well region has a greater depth than the body region.

6. The semiconductor device according to claim 4, wherein the first well region of the first conductivity type has substantially the same depth as the body region.

7. The semiconductor device according to claim 4, wherein the second well region of the second conductivity type has substantially the same depth as the body region.

8. The semiconductor device according to claim 4, wherein the first well region of the first conductivity type and the second well region of the second conductivity type have substantially the same depth as the body region.

9. The semiconductor device according to claim 1, wherein a deepest portion of the trench reaches the semiconductor layer of the first conductivity type.

10. The semiconductor device according to claim 1, further comprising a body contact region of the second conductivity type formed in the source region.

11. The semiconductor device according to claim 1, further comprising a body contact region of the second conductivity type formed at a center of the source region to penetrate the source region.

12. The semiconductor device according to claim 1, wherein at least the peripheral wall film is interposed between the gate electrode and the source region.

13. The semiconductor device according to claim 1, wherein a bottom portion of the body region has an impurity concentration substantially identical to that of a surface layer portion of the body region.