Three-dimensional integrated circuits and techniques for fabrication thereof

• US 8,426,921 B2
• Filed: 02/01/2011
• Issued: 04/23/2013
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Assefa, Solomon, Chen, Kuan-Neng, Koester, Steven J., Vlasov, Yuri A.
• Primary Examiner(s): Sefer, A.
• Application Number:
  US13/019,130
• Publication Number:
  US 20110133281A1
• Time in Patent Office: 812 Days
• Field of Search: 257350-351
• US Class Current: 257/350
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/144 Devices controlled by radiation

Abstract

Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Claims

1. A three-dimensional integrated circuit comprising:

a bottom device layer having a substrate, a digital complementary metal-oxide semiconductor (CMOS) circuitry layer adjacent to the substrate and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate; and

a top device layer having an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer,

wherein the bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

2. The integrated circuit of claim 1, further comprising:

one or more inter-layer conductive vias interconnecting the top device layer and the bottom device layer.

3. The integrated circuit of claim 1, wherein the digital CMOS circuitry layer comprises a plurality of digital CMOS logic components.

4. The integrated circuit of claim 3, wherein the digital CMOS circuitry layer comprises one or more metal pads associated therewith connected to one or more of the digital CMOS logic components by way of intra-layer conductive vias.

5. The integrated circuit of claim 1, wherein the analog CMOS and photonics circuitry layer comprises one or more of analog modulators, analog drivers, analog transimpedance amplifiers, optical waveguides, optical detectors, switches and optical couplers.

6. The integrated circuit of claim 5, wherein the analog CMOS and photonics circuitry layer comprises one or more metal pads associated therewith connected to one or more of the analog modulators, the analog drivers, the analog transimpedance amplifiers, the optical waveguides, the optical detectors, the switches and the optical couplers by way of intra-layer conductive vias.

7. The integrated circuit of claim 1, wherein the digital CMOS circuitry layer is formed in an SOI layer adjacent to the substrate.

8. The integrated circuit of claim 1, wherein the substrate comprises one or more of gallium arsenide, silicon germanium and glass.

9. The integrated circuit of claim 1, wherein the substrate comprises a silicon carrier substrate.

10. The integrated circuit of claim 1, wherein the BOX has a thickness of greater than or equal to about one micrometer.

11. A three-dimensional integrated circuit comprising:

a bottom device layer having a substrate, a digital CMOS circuitry layer adjacent to the substrate and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate; and

a top device layer having an analog CMOS and photonics circuitry layer formed in a SOI layer having a BOX with a thickness of greater than or equal to about 0.5 micrometers, at least one semiconductor optical amplifier bonded to the analog CMOS and photonics circuitry layer by an oxide-to-oxide bond and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer,

wherein the bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

12. The integrated circuit of claim 11, further comprising:

one or more inter-layer conductive vias interconnecting the top device layer and the bottom device layer.

13. The integrated circuit of claim 12, wherein at least one of the inter-layer conductive vias extends through the substrate.