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Edge connect wafer level stacking

  • US 8,426,957 B2
  • Filed: 04/14/2011
  • Issued: 04/23/2013
  • Est. Priority Date: 10/10/2006
  • Status: Active Grant
First Claim
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1. A stacked microelectronic assembly, comprising:

  • a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly, each stacked subassembly including at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element, each of the first and second microelectronic elements having edges extending away from the respective faces, each of the first and second stacked subassemblies having a land exposed at a face of the subassembly and a lead, the lead coupled to the land and extending along the face of the subassembly and from the face of the subassembly continuously about the edges of the first and second microelectronic elements thereof; and

    a bond wire conductively connecting the land of the first stacked subassembly with the land of the second stacked subassembly.

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