Stacked chip package with redistribution lines

• US 8,426,958 B2
• Filed: 06/13/2011
• Issued: 04/23/2013
• Est. Priority Date: 05/03/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lin, Shih-Hsiung, Lo, Hsin-Jung, Chen, Ying-Chih, Chou, Chiu-Ming
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US13/159,368
• Publication Number:
  US 20110241183A1
• Time in Patent Office: 680 Days
• Field of Search: 257/686, 257/685, 257/777, 257/E25.006, 257/E25.021, 257/E25.027, 257/E23.085, 257/693, 257/698
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Claims

1. A chip package comprising:

a glass substrate;

multiple solder balls under said glass substrate;

a first pad under said glass substrate;

a first chip over said glass substrate;

a first interconnect passing through an opening in said glass substrate and connecting said first chip to said first pad;

a second interconnect connected to said first chip and disposed over said glass substrate, wherein said second interconnect is connected to said first pad through said first interconnect; and

a second chip over said first chip and said glass substrate.

2. The chip package of claim 1 further comprising a second pad over said glass substrate and a second interconnect connecting said second chip to said second pad.

3. The chip package of claim 2, wherein said second interconnect comprises a wirebonded wire.

4. The chip package of claim 1 wherein said first chip comprises a second pad having a bottom surface connected to said first interconnect.

5. The chip package of claim 1, wherein said second interconnect comprises a copper layer.

6. The chip package of claim 1, wherein said second interconnect comprises a gold layer.

7. The chip package of claim 1, wherein said second interconnect comprises a nickel layer.

8. The chip package of claim 1, wherein said second interconnect comprises an aluminum layer.

9. The chip package of claim 1, wherein said second chip joins said first chip.

10. The chip package of claim 1, further comprising a polymer portion over said glass substrate and said first and second chips, wherein said polymer portion covers a sidewall of said first chip and a sidewall of said second chip.

11. The chip package of claim 1 further comprising a polymer portion in said opening, wherein said polymer portion encloses said first interconnect.

12. A chip package comprising:

a glass substrate;

multiple solder balls under said glass substrate;

a first pad under said glass substrate;

a first chip over said glass substrate, wherein said first chip comprises a passivation layer comprising a nitride, a second pad having a contact point at a top of a first opening in said passivation layer, and a first interconnect over said glass substrate, wherein said first interconnect is connected to said contact point through said first opening, wherein said first interconnect comprises a copper layer having a thickness between 1 and 30 micrometers; and

a second interconnect passing through a second opening in said glass substrate and connecting said first interconnect to said first pad, wherein said contact point is connected to said first pad through, in sequence, said first interconnect and said second interconnect.

13. The chip package of claim 12 further comprising a second chip over said first chip and said glass substrate.

14. The chip package of claim 13 further comprising a third pad over said glass substrate and a third interconnect connecting said second chip to said third pad.

15. The chip package of claim 14, wherein said third interconnect comprises a wirebonded wire.

16. The chip package of claim 13, wherein said second chip joins said first chip.

17. The chip package of claim 12 further comprising a polymer portion over said glass substrate and said first chip, wherein said polymer portion covers a sidewall of said first chip.

18. The chip package of claim 12 further comprising a polymer portion in said opening, wherein said polymer portion encloses said second interconnect.

19. A chip package comprising:

a glass substrate;

multiple solder balls under said glass substrate;

a first pad under said glass substrate;

a first chip over said glass substrate, wherein said first chip comprises a passivation layer comprising a nitride, a second pad having a contact point at a top of a first opening in said passivation layer, and a first interconnect over said glass substrate, wherein said first interconnect is connected to said contact point through said first opening, wherein said first interconnect comprises a gold layer; and

a second interconnect passing through a second opening in said glass substrate and connecting said first interconnect to said first pad, wherein said contact point is connected to said first pad through, in sequence, said first interconnect and said second interconnect.

20. The chip package of claim 19 further comprising a second chip over said first chip and said glass substrate.

21. The chip package of claim 20 further comprising a third pad over said glass substrate and a third interconnect connecting said second chip to said third pad.

22. The chip package of claim 21, wherein said third interconnect comprises a wirebonded wire.

23. The chip package of claim 20, wherein said second chip joins said first chip.

24. The chip package of claim 19 further comprising a polymer portion over said glass substrate and said first chip, wherein said polymer portion covers a sidewall of said first chip.

25. The chip package of claim 19 further comprising a polymer portion in said opening, wherein said polymer portion encloses said second interconnect.

26. The chip package of claim 19, wherein said gold layer has a thickness between 1 and 15 micrometers.