Embedded 3D interposer structure

• US 8,426,961 B2
• Filed: 06/25/2010
• Issued: 04/23/2013
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shih, Ying-Ching, Lin, Jing-Cheng, Chiou, Wen-Chih, Jeng, Shin-Puu, Yu, Chen-Hua
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US12/823,851
• Publication Number:
  US 20110316147A1
• Time in Patent Office: 1,033 Days
• Field of Search: 257/621, 257/737, 257/692, 257/746, 257/774
• US Class Current: 257/698
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2203/016 : Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
• CPC Class Codes: H05K 2203/025 : Abrading, e.g. grinding or sand blasting deburring, rounding, bevelling or smoothing conductor edges H05K2203/0346
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Claims

1. A device comprising:

an interposer comprising;

a substrate;

at least one dielectric layer over the substrate;

a plurality of through-substrate vias (TSVs) penetrating the substrate;

a first metal bump in the at least one dielectric layer and electrically coupled to the plurality of TSVs; and

a second metal bump over the at least one dielectric layer; and

a first die embedded in the at least one dielectric layer and bonded to the first metal bump through a metal connector of the first die, and the metal connector of the first die faces away from the substrate.

2. The device of claim 1, further comprising a second die bonded to the second metal bump, wherein the first die is disposed between the substrate and the second die.

3. The device of claim 2, wherein the first die further comprises a TSV therein, with the TSV in the first die being electrically coupled to one of the plurality of TSVs in the substrate of the interposer.

4. The device of claim 1, wherein the interposer comprises a silicon substrate.

5. The device of claim 1, wherein the interposer comprises active devices at a surface of the substrate.

6. The device of claim 1, wherein the interposer comprises a dielectric substrate.

7. The device of claim 1, wherein the second metal bump is directly over the first die, and is electrically coupled to the first die.

8. The device of claim 1, further comprising a via in the at least one dielectric layer and electrically coupling the second metal bump to one of the plurality of TSVs, wherein the via extends from a level higher than a top surface of the first die to a level lower than a bottom surface of the first die.

9. The device of claim 1, wherein the substrate comprises a recess, with at least a portion of the first die located in the recess.

10. A device comprising:

a first die;

an interposer comprising;

a substrate;

a first plurality of through-substrate vias (TSVs) penetrating the substrate;

a first plurality of redistribution lines (RDLs) over the substrate and electrically coupled to the first plurality of TSVs;

a dielectric layer over the top surface of the substrate, with the first die being in the dielectric layer, wherein the dielectric layer comprises a portion directly over the first die, and a second portion encircling the first die; and

a plurality of vias extending into the dielectric layer, wherein the plurality of vias comprises a first portion directly over and electrically coupled to the first die, and a second portion vertically misaligned with the first die and electrically coupled to a portion of the first plurality of TSVs, and wherein top ends of the plurality of vias are level with each other;

a first plurality of metal bumps over the dielectric layer and electrically coupled to the plurality of vias, wherein the first plurality of metal bumps comprises a portion electrically coupled to the first die; and

a second die over and bonded to the first plurality of metal bumps.

11. The device of claim 10, further comprising a second plurality of metal bumps bonded to the interposer, wherein the first and the second plurality of metal bumps are on opposite sides of the interposer.

12. The device of claim 10, wherein the substrate of the interposer comprises a recess, and wherein a portion of the first die is located in the recess.

13. The device of claim 10, wherein the first die further comprises a second plurality of TSVs, and wherein one of the second plurality of TSVs is electrically coupled to one of the first plurality of TSVs.

14. The device of claim 10, further comprising a molding compound over and encircling the second die.

15. The device of claim 10, further comprising an adhesive contacting a bottom surface of the second die, wherein the second die comprises a metal connector at a top surface of the second die, and wherein the metal connector is connected to one of the first plurality of metal bumps.

16. A device comprising:

an interposer substantially free from integrated circuit devices, wherein the interposer comprises;

a silicon substrate;

a first plurality of through-substrate vias (TSVs) in the substrate;

a first plurality of metal bumps on a first side of the interposer, with a portion of the first plurality of metal bumps electrically coupled to the first plurality of TSVs;

a second plurality of metal bumps on a second side of the interposer opposite the first side, wherein the second plurality of metal bumps is electrically coupled to the first plurality of TSVs;

a first interconnect structure on the first side of the interposer and comprising;

at least one dielectric layer over the silicon substrate; and

redistribution lines in the at least one dielectric layer and electrically coupled between the first plurality of metal bumps and the first plurality of TSVs;

a first die embedded in the at least one dielectric layer and under the first plurality of metal bumps, wherein the first die is electrically coupled to the first plurality of metal bumps; and

a second die over and bonded to the first plurality of metal bumps.

17. The device of claim 16 further comprising a plurality of vias in the at least one dielectric layer and comprising:

a first via electrically coupling the first plurality of metal bumps to the first die; and

a second via electrically coupling the first plurality of metal bumps to the first plurality of TSVs.

18. The device of claim 16, further comprising a package substrate bonded to the interposer through the second plurality of metal bumps.

19. The device of claim 16, wherein a recess extends from a top surface of the silicon substrate into the silicon substrate, wherein the at least one dielectric layer extends into the recess, and wherein a portion of the first die is located in the recess.

20. The device of claim 16, wherein the first die comprises a second plurality of TSVs therein and electrically coupling the second die to the second plurality of metal bumps.

21. The device of claim 16, further comprising a molding compound over and encircling the second die.