Power semiconductor package structure and manufacturing method thereof

• US 8,426,963 B2
• Filed: 04/11/2011
• Issued: 04/23/2013
• Est. Priority Date: 01/18/2011
• Status: Active Grant

• Current Assignee: Delta Electronics Incorporated
• Original Assignee: Delta Electronics Incorporated
• Inventors: Zeng, Jian-Hong, Hong, Shou-Yu
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/084,292
• Publication Number:
  US 20120181706A1
• Time in Patent Office: 743 Days
• Field of Search: 257/688, 257/689, 257/690, 257/692, 257/693, 257/695, 257/723, 257/724, 257/735, 257/736, 257/777, 438/109, 438/611, 438/666
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32155 the item being non-metallic, e.g. being an insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/071 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode. The second conductive sheet is electrically connected to the third main power electrode. The third conductive sheet is electrically connected to the first control electrode. At least a part of the first control electrode is non-covered by the second power chip along a projection direction, which is perpendicular to the carrier.

Claims

1. A power semiconductor package structure, comprising:

a carrier;

a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode;

a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip;

a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode;

a second conductive sheet electrically connected to the third main power electrode; and

a third conductive sheet electrically connected to the first control electrode;

wherein, at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier.

3. The power semiconductor package structure of claim 1, wherein the entire first control electrode is non-covered by the second power chip along the projection direction perpendicular to the carrier.

4. The power semiconductor package structure of claim 1, wherein the second power chip further comprises:

a second control electrode disposed on the third surface; and

a fourth conductive sheet electrically connected to the second control electrode.

5. The power semiconductor package structure of claim 4, wherein each of the first conductive sheet, the second conductive sheet, the third conductive sheet, and the fourth conductive sheet is a metal sheet.

6. The power semiconductor package structure of claim 4, wherein at least one of the first conductive sheet, the second conductive sheet, the third conductive sheet, and the fourth conductive sheet has a recess.

7. The power semiconductor package structure of claim 4, wherein at least one of the first conductive sheet, the second conductive sheet, the third conductive sheet, and the fourth conductive sheet has a plurality of bending portions.

8. The power semiconductor package structure of claim 4, further comprising:

a molding compound covering the first power chip, the second power chip, a part of the carrier, a part of the first conductive sheet, a part of the second conductive sheet, a part of the third conductive sheet, and a part of the fourth conductive sheet, wherein at least one of the first conductive sheet, the second conductive sheet, the third conductive sheet, and the fourth conductive sheet is not electrically connected with the carrier and protruded out of the molding compound.

9. The power semiconductor package structure of claim 4, wherein the third conductive sheet has a step shape, and one end portion of the third conductive sheet connecting to the first control electrode has a thickness smaller than that of other portions thereof.

13. The power semiconductor package structure of claim 4, further comprising:

a third power chip having a fifth surface and a sixth surface opposing to the fifth surface, wherein a third control electrode and a fifth main power electrode are disposed on the fifth surface, a sixth main power electrode is disposed on the sixth surface, and the sixth surface is disposed on the carrier and electrically connected to the carrier through the sixth main power electrode;

a fourth power chip having a seventh surface and an eighth surface opposing to the seventh surface, wherein a fourth control electrode and a seventh main power electrode are disposed on the seventh surface, an eighth main power electrode is disposed on the eighth surface, and the eighth surface is disposed on the third power chip; and

a fifth conductive sheet electrically connected to the fifth main power electrode and the eighth main power electrode;

wherein the second conductive sheet is electrically connected with the third main power electrode and the seventh main power electrode.

14. The power semiconductor package structure of claim 4, further comprising:

a supporter disposed between the carrier and the second power chip for supporting the second power chip.

2. A power semiconductor package structure, comprising:

a carrier;

a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode;

a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip;

a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode; and

a second conductive sheet electrically connected to the third main power electrode;

wherein, the dimension of the second power chip is not smaller than that of the first power chip, and at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier.

10. The power semiconductor package structure of claim 2, wherein the second power chip further comprising:

a second control electrode disposed on the third surface;

a first electronic connector electrically connecting to the first control electrode; and

a second electronic connector electrically connecting to the second control electrode.

11. The power semiconductor package structure of claim 10, wherein each of the first conductive sheet and the second conductive sheet is a metal sheet, and each of the first electronic connector and the second electronic connector is a bonding wire.

12. The power semiconductor package structure of claim 10, wherein at least one of the first conductive sheet and the second conductive sheet has a recess.

15. The power semiconductor package structure of claim 10, further comprising:

a third power chip having a fifth surface and a sixth surface opposing to the fifth surface, wherein a third control electrode and a fifth main power electrode are disposed on the fifth surface, a sixth main power electrode is disposed on the sixth surface, and the sixth surface is disposed on the carrier and electrically connected to the carrier through the sixth main power electrode;

a fourth power chip having a seventh surface and an eighth surface opposing to the seventh surface, wherein a fourth control electrode and a seventh main power electrode are disposed on the seventh surface, an eighth main power electrode is disposed on the eighth surface, and the eighth surface is disposed on the third power chip; and

a fifth conductive sheet electrically connected to the fifth main power electrode and the eighth main power electrode;

wherein the second conductive sheet is electrically connected with the third main power electrode and the seventh main power electrode.

16. The power semiconductor package structure of claim 10, further comprising:

a supporter disposed between the carrier and the second power chip for supporting the second power chip.

17. A manufacturing method of a power semiconductor package structure, comprising steps of:

disposing a first power chip on a carrier, wherein the first power chip has a first control electrode;

disposing a first conductive sheet on the first power chip;

disposing a second power chip on the first conductive sheet, wherein at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier;

disposing a second conductive sheet on the second power chip;

disposing a third conductive sheet to electrically connecting with the first control electrode of the first power chip;

disposing a fourth conductive sheet to electrically connecting with the second power chip; and

disposing a molding compound to cover the first power chip and the second power chip.

18. The manufacturing method of claim 17, wherein the carrier comprises a plurality of carrying units arranged in matrix, and a plurality of the first power chips are disposed on the carrying units respectively.

19. The manufacturing method of claim 18, wherein the first conductive sheet and the third conductive sheet are integrally formed as one piece to form a plurality of first electronic connecting units arranged in matrix, the second conductive sheet and the fourth conductive sheet are integrally formed as one piece to form a plurality of second electronic connecting units arranged in matrix, and the first electronic connecting units and the second electronic connecting units are disposed corresponding to the carrying units respectively.

20. The manufacturing method of claim 19, wherein the molding compound covers the carrying units, the first electronic connecting units, and the second electronic connecting units.

21. The manufacturing method of claim 20, wherein the carrying units, the first electronic connecting units, and the second electronic connecting units comprise a plurality of cutting channels respectively, and the cutting channels are relatively disposed between the carrying units, the first electronic connecting units, and the second electronic connecting units, so that the power semiconductor package structure is separated based on the cutting channels.