Structure and manufacturing method of chip scale package

• US 8,426,982 B2
• Filed: 07/30/2009
• Issued: 04/23/2013
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Huang, Ching-Cheng, Lin, Mou-Shiung
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/512,073
• Publication Number:
  US 20090289346A1
• Time in Patent Office: 1,363 Days
• Field of Search: 257/678, 257/738, 257/778, 257/781, 257/E21.503, 257/E21.508, 257/E23.021, 257/E21.511, 438/106, 438/108, 438/614
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Claims

1. A chip package comprising:

a die having a contact pad on a top side of said die, a single barrier metal layer being disposed on said contact pad;

a substrate having a bottom side joining a top side of said die, wherein said substrate is over said die and across a left outer sidewall of said die and a right outer sidewall of said die, said substrate having an opening passing through said substrate;

a metal bump on said substrate, a portion of said metal bump passing through said opening, said metal bump having a bottom end contacting said contact pad via said single barrier metal layer; and

a molding material under a bottom side of said die, at left and right sides of said die and under said bottom side of said substrate, wherein said molding material has a left outer sidewall and a right outer sidewall substantially parallel with said left outer sidewall of said molding material, said left and right outer sidewalls of said molding material being directly adjacent and parallel to said left and right sides of said die, wherein said substrate has a left outer sidewall substantially aligned with said left outer sidewall of said molding material and a right outer sidewall substantially aligned with said right outer sidewall of said molding material, wherein said molding material comprises a first portion between said left outer sidewall of said molding material and said left side of said die, a second portion between said right outer sidewall of said molding material and said right side of said die, and a third portion vertically under said bottom side of said die and between said first and second portions, wherein said first, second and third portions continuously extend under said die.

2. The chip package of claim 1, wherein said substrate comprises a ball-grid-array (BGA) substrate.

3. The chip package of claim 1, wherein said die comprises a passivation layer at said top side of said die, wherein a second opening is provided in said passivation layer over a contact point of said contact pad, and said contact point is at a bottom of said second opening, and said single barrier metal layer is at said top side of said die and over said passivation layer and said contact point, wherein said single barrier metal layer is connected to said contact point through said second opening, wherein said metal bump is over said single barrier metal layer.

4. The chip package of claim 3, wherein said single barrier metal layer comprises nickel.

5. The chip package of claim 3, wherein said single barrier metal layer comprises copper.

6. The chip package of claim 1, wherein said substrate comprises bismaleimide triazine (BT).

7. The chip package of claim 1, wherein said metal bump comprises a tin-silver alloy.

8. The chip package of claim 1, wherein said die comprises a copper pad at said top side of said die and vertically under said metal bump.

9. The chip package of claim 1, wherein said die comprises an aluminum pad at said top side of said die and vertically under said metal bump.

10. The chip package of claim 1, wherein said metal bump comprises tin.

29. The chip package of claim 1, wherein said metal bump comprises a tin-lead alloy.

11. A chip package comprising:

a first substrate having a first opening that passes through said first substrate;

a second substrate comprising a die sawed from a wafer and being disposed over said first substrate, wherein said first opening in said first substrate is under a bottom side of said second substrate, wherein said second substrate comprises a contact pad and a separating layer at said bottom side of said second substrate, wherein a second opening in said separating layer is under a contact point of said contact pad, and said contact point is at a top of said second opening, wherein a single barrier metal layer is under said contact point of said contact pad;

a metal interconnect under said second substrate, a first portion of said metal interconnect being disposed in said first opening in said first substrate, wherein said first portion of said metal interconnect contacts a sidewall of said first opening, wherein a second portion of said metal interconnect contacts said contact point via said single barrier metal layer through said second opening; and

a molding material over a top side of said second substrate, and at left and right sides of said second substrate, wherein said molding material has a left outer sidewall and a right outer sidewall substantially parallel with said left outer sidewall of said molding material, said left and right outer sidewalls of said molding material being directly adjacent and parallel to said left and right sides of said die, wherein said first substrate has a left outer sidewall substantially aligned with said left outer sidewall of said molding material and a right outer sidewall substantially aligned with said right outer sidewall of said molding material, wherein said molding material comprises a first portion between said left outer sidewall of said molding material and said left side of said second substrate, a second portion between said right outer sidewall of said molding material and said right side of said second substrate, and a third portion vertically over said top side of said second substrate and between said first and second portions, wherein said first, second and third portions continuously extend over said second substrate.

12. The chip package of claim 11, wherein said contact pad comprises a copper pad.

13. The chip package of claim 11, wherein said contact pad comprises an aluminum pad.

14. The chip package of claim 11, wherein said first opening is vertically under said contact point.

15. The chip package of claim 11, wherein said first substrate comprises bismaleimide triazine (BT).

16. The chip package of claim 11, wherein said first opening is under said single barrier metal layer.

17. The chip package of claim 16, wherein said single barrier metal layer comprises copper.

18. The chip package of claim 16, wherein said single barrier metal layer comprises nickel.

19. The chip package of claim 11 further comprising an adhesive material between said first substrate and said second substrate.

20. A chip package comprising:

a first substrate having a first opening that passes through said first substrate;

a second substrate comprising a die and being disposed over said first substrate, and joining said first substrate, wherein said first opening in said first substrate is under a bottom side of said second substrate, wherein said second substrate comprises a copper pad and a separating layer at said bottom side of said second substrate, wherein a second opening in said separating layer is under a contact point of said copper pad, and said contact point is at a top of said second opening, wherein a single barrier metal layer is under and on said contact point of said contact pad; and

a metal interconnect under said second substrate, a first portion of said metal interconnect being disposed in said first opening in said first substrate, wherein a second portion of said metal interconnect contacts said contact point via said single barrier metal layer through said second opening; and

a molding material over a top side of said second substrate, and at left and right sides of said second substrate, wherein said molding material has a left outer sidewall and a right outer sidewall substantially parallel with said left outer sidewall of said molding material, said left and right outer sidewalls of said molding material being directly adjacent and parallel to said left and right sides of said die, wherein said first substrate has a left outer sidewall substantially aligned with said left outer sidewall of said molding material and a right outer sidewall substantially aligned with said right outer sidewall of said molding material, wherein said molding material comprises a first portion between said left outer sidewall of said molding material and said left side of said second substrate, a second portion between said right outer sidewall of said molding material and said right side of said second substrate, and a third portion vertically over said top side of said second substrate and between said first and second portions, wherein said first, second and third portions continuously extend over said second substrate.

21. The chip package of claim 20, wherein said first opening is vertically under said contact point.

22. The chip package of claim 20, wherein said single barrier metal layer is connected to said contact point through said second opening, wherein said first opening is under said single barrier metal layer.

23. The chip package of claim 22, wherein said single barrier metal layer comprises nickel.

24. The chip package of claim 22, wherein said single barrier metal layer comprises copper.

25. The chip package of claim 20, wherein said first portion of said metal interconnect contacts a sidewall of said first opening.

26. The chip package of claim 20, wherein said first substrate comprises bismaleimide triazine (BT).

27. The chip package of claim 20, wherein said second substrate comprises a die.

28. The chip package of claim 20 further comprising an adhesive material between said first substrate and said second substrate.