High efficiency, high frequency amplifiers

• US 8,427,241 B2
• Filed: 05/24/2011
• Issued: 04/23/2013
• Est. Priority Date: 05/24/2011
• Status: Active Grant

• Current Assignee: Amcom Communications, Inc.
• Original Assignee: Amcom Communications, Inc.
• Inventors: Ezzeddine, Amin, Huang, Ho C.
• Primary Examiner(s): Choe, Henry
• Application Number:
  US13/068,905
• Publication Number:
  US 20120299658A1
• Time in Patent Office: 700 Days
• Field of Search: 330/124.R, 330/295, 330/302, 330/310, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/423 with MOSFET's

Abstract

The invention is an improvement in microwave and millimeter wave amplifiers. Capacitors are connected in parallel with the source and drain terminals of all of the amplifying elements in a series of such elements except the first, compensating for current leakage due to gate capacitance. This results in improved synchronism of the amplifying elements, and improved overall efficiency and circuit performance.

Claims

1. An amplifier for amplifying an input signal, comprising:

a plurality of semiconductor amplifying elements, each comprising a control terminal to which a signal may be applied for controlling the flow of current between additional input and output terminals, and a source of bias voltage providing power for said amplifying elements,

said plurality of amplifying elements being connected in series, such that the output terminal of a first element of the series is connected to the input terminal of the next element of the series, and so on, the input signal being applied to the control terminal of the first element of the series, and the output terminal of the last element of the series being connected to an output circuit,

wherein capacitors are connected between the control terminals of each of the amplifying elements in the series, except the first, and ground, the value of each said capacitor being chosen to optimize the impedance of and power output by the corresponding amplifying elements;

wherein capacitors are connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first, whereby current leaking due to control terminal capacitance is compensated for, and the amplifying elements operate in substantial synchronism; and

wherein the values of said capacitors connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first are chosen such that the voltage swings across the corresponding amplifying elements, the current gain provided by the corresponding amplifying elements, and the current flowing through the corresponding amplifying elements are substantially equal.

2. The amplifier of claim 1, wherein the input control terminal of the first of said amplifying elements of the series is connected to a point maintained at a fixed potential through a choke, such that high-frequency input signal components are not grounded.

3. The amplifier of claim 1, further comprising an input matching network between the input terminal of said amplifier and the control terminal of the first amplifying element in said series, and an output matching network between the output terminal of the last amplifying element in the series and the output terminal of said amplifier.

4. The amplifier of claim 3, wherein said input and output matching networks comprise DC blocking capacitors.

5. The amplifier of claim 1, wherein the value C_g, _Mof each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_M-₁ of the corresponding amplifying element, in accordance with the following equation:

6. The amplifier of claim 1, wherein said source of bias voltage is connected to the output terminal of the last of said elements in said series through a choke, and wherein said bias voltage is provided to each of said elements by voltage-dividing resistors in series across the control terminals of said elements.

7. The amplifier of claim 6, wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through the same series-connected resistors used to supply bias voltage.

24. The amplifier of claim 1, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are:

25. The amplifier of claim 1, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are approximated as:

8. A circuit for providing high-power, high-impedance amplification of a RF signal, comprising:

a plurality of amplifying elements, each comprising input, output, and control terminals,

said plurality of amplifying elements being connected in series, such that the output terminal of the first element in the series is connected to the input terminal of the second, and so on;

an input connection for applying a RF input signal to the control terminal of the first element in the series;

an output connection connected to the output terminal of the last element in the series, for applying an amplified RF output signal to a load;

a source of bias voltage operatively connected to each of said amplifying elements;

capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground, the value of each said capacitor being chosen to optimize the impedance of and power output by the corresponding amplifying element;

capacitors connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first, whereby current leaking due to control terminal capacitance is compensated for, and the amplifying elements operate in substantial synchronism; and

wherein the values of said capacitors connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first are chosen such that the voltage swings across the corresponding amplifying elements, the current gain provided by the corresponding amplifying elements, and the current flowing through the corresponding amplifying elements are substantially equal.

9. The circuit of claim 8, wherein said source of bias voltage is connected to the output terminal of the last of said elements in said series through a choke.

10. The circuit of claim 8, further comprising an input matching network between said input connection and the control terminal of the first amplifying element in said series, and an output matching network between the output terminal of the last amplifying element in the series and said output connection.

11. The circuit of claim 10, wherein said input and output matching networks comprise DC blocking capacitors.

12. The circuit of claim 8, wherein the value C_g,M of each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_M−

1 of the corresponding amplifying element, in accordance with the following equation;

13. The circuit of claim 8, wherein said bias voltage is provided to each of said elements by voltage-dividing resistors in series across the control terminals of said elements.

14. The circuit of claim 13, wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through the same series-connected resistors used to supply bias voltage.

26. The circuit of claim 8, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are:

27. The circuit of claim 8, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are approximated as:

15. A method for providing high-power, high-impedance amplification of an RF input signal, comprising the steps of:

connecting a plurality of amplifying elements, each comprising input, output, and control terminals, in series, such that the output terminal of the first element in the series is connected to the input terminal of the second, and so on;

applying an RF input signal to the control terminal of the first element in the series;

providing bias voltage to each of said amplifying elements, such that the input RF signal is amplified in each element;

connecting a load to the output terminal of the last element in the series, for applying an amplified RF output signal to the load; and

wherein capacitors are connected between the control terminals of each of said amplifying elements, except the first, and ground, the value of each of said capacitors being chosen to adjust the impedance of and power output by the corresponding amplifying element;

wherein capacitors are connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first, whereby current leaking due to control terminal capacitance is compensated for, and the amplifying elements operate in substantial synchronism; and

wherein the values of said capacitors connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first are chosen such that the voltage swings across the corresponding amplifying elements, the current gain provided by the corresponding amplifying elements, and the current flowing through the corresponding amplifying elements are substantially equal.

16. The method of claim 15, wherein the value C_g,M of each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_M−

1 of the corresponding amplifying element, in accordance with the following equation;

17. The method of claim 16, wherein

28. The method of claim 15, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are:

29. The method of claim 15, wherein the values C_d,M of the capacitors connected in parallel across the input and output terminals of the M^th amplifying element in the series except the first are approximated as:

18. An amplifier for amplifying an input signal, comprising:

a plurality of bipolar transistor amplifying elements, each comprising a base terminal to which a signal may be applied for controlling the flow of current between additional input and output terminals, and a source of base current providing power for said amplifying elements,

said plurality of amplifying elements being connected in series, such that the output terminal of a first element of the series is connected to the input terminal of the next element of the series, and so on, the input signal being applied to the base terminal of the first element of the series, and the output terminal of the last element of the series being connected to an output circuit,

wherein capacitors are connected between the base terminals of each of the amplifying elements in the series except the first and ground, the value of each said capacitor being chosen to optimize the impedance of and power output by the corresponding amplifying elements;

wherein said source of base current is connected to the output terminal of the last of said elements in said series through a choke, and wherein said base current is provided to the base terminal of each of said elements by current-controlling resistors in series with the base terminals of said elements;

wherein capacitors are connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first, whereby current leaking due to control terminal capacitance is compensated for, and the amplifying elements operate in substantial synchronism, and

wherein the values of said capacitors connected in parallel across the input and output terminals of each of the amplifying elements in the series except the first are chosen such that the voltage swings across the corresponding amplifying elements, the current gain provided by the corresponding amplifying elements, and the current flowing through the corresponding amplifying elements are substantially equal.

19. The amplifier of claim 18, wherein the base terminal of the first of said amplifying elements of the series is connected to a point maintained at a fixed potential through a choke, such that high-frequency input signal components are not grounded.

20. The amplifier of claim 18, further comprising an input matching network between the input terminal of said amplifier and the base terminal of the first amplifying element in said series, and an output matching network between the output terminal of the last amplifying element in the series and the output terminal of said amplifier.

21. The amplifier of claim 18, wherein said input and output matching networks each comprise capacitors.

22. The amplifier of claim 18, wherein the base current is supplied separately to each of said amplifying elements.

23. The amplifier of claim 18, wherein the value C_g,M of each of said capacitors connected between the base terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_M−

1 of the corresponding amplifying element, in accordance with the following equation;

Z_source=1/g_m*(C_be+C_shunt)/C_shunt

where Z_source is the source input impedance of each amplifying element;

g_m is the bipolar element'"'"'s transconductance;

C_be is the base-to-emitter capacitance of the bipolar element; and

C_shunt is the shunt capacitance between base and ground.