Nonvolatile memory device, memory system incorporating same, and method of operating same

• US 8,427,871 B2
• Filed: 06/22/2010
• Issued: 04/23/2013
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Jinman, Yoon, Sangyong
• Primary Examiner(s): Le, Toan
• Assistant Examiner(s): PHAM, HAI Q
• Application Number:
  US12/820,435
• Publication Number:
  US 20110051514A1
• Time in Patent Office: 1,036 Days
• Field of Search: 365/185.09, 365/185.22, 365/185.29, 365/185.17, 365/185.18
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits.

Claims

1. A method of performing a program operation in a nonvolatile memory device, comprising:

(a) applying a program pulse to selected memory cells;

(b) detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits; and

(c) determining a program completion status of the program operation based on the number of detected fail bits,

wherein the disturbed inhibit bits include at least one disturbed inhibit bit among erase bits or at least one disturbed inhibit bit among passed program bits.

2. The method of claim 1, wherein (b) comprises detecting the number of failed program bits and disturbed program bits simultaneously.

3. The method of claim 1, further comprising:

repeating (a), (b), and (c) until the detected number of failed bits falls below a predetermined reference value.

4. The method of claim 1, further comprising:

performing a plurality of program loops each comprising (a), (b), and (c) until a detected number of fail bits in a current program loop increases relative to a detected number of fail bits in a previous program loop.

5. The method of claim 1, wherein the program operation is completed upon determining that the number of detected fail bits is less than or equal to a reference value.

6. The method of claim 5, wherein the reference value changes according to a number of program or erase operations that have been performed previously on a memory block containing the selected memory cells.

7. The method of claim 6, wherein the reference value decreases as the number of program or erase operations increases.

8. The method of claim 5, wherein the reference value corresponds to a number of bits that can be corrected through the use of an error correction code.

9. The method of claim 1, further comprising:

performing a plurality of program loops each comprising (a), (b), and (c), and designating the program operation as a failure upon determining that a predetermined number of program loops have been performed and the number of fail bits remains above another predetermined value.

10. The method of claim 1, wherein the nonvolatile memory device is a flash memory device.

11. The method of claim 10, wherein the nonvolatile memory device is a multi-level cell flash memory device.

12. The method of claim 1, wherein (b) further comprises detecting fail bits in each of a plurality of sectors of the selected memory cells, and (c) further comprises determining the program completion status based on a number of fail bits in each of the sectors.

13. A nonvolatile memory device comprising:

a page buffer circuit configured to store program bits and inhibit bits to be programmed in selected memory cells in a program operation, and further configured to perform a program verify operation to detect failed program bits and disturbed inhibit bits from the selected memory cells; and

a control logic configured to determine a completion state of the program operation based on the number of detected failed program bits and disturbed inhibit bits,

wherein the disturbed inhibit bits include at least one disturbed inhibit bit among erase bits or at least one disturbed inhibit bit among passed program bits.

14. The nonvolatile memory device of claim 13, wherein the page buffer circuit comprises a plurality of page buffers, and each of the plurality of page buffers comprises an inhibit data latch for storing inhibit bit data, and a sense latch for storing data indicating a program state of a corresponding one of the selected memory cells,

wherein each of the plurality of page buffers is configured to compare the stored inhibit bit data with the data stored in the sense latch to determine a program status of the corresponding one of the selected memory cells.

15. The nonvolatile memory device of claim 14, wherein the sense latch is configured to store a fail bit to indicate whether the corresponding one of the selected memory cells has been successfully programmed, and to output a fail bit upon determining that the corresponding one of the selected memory cells has not been successfully programmed;

and

wherein each of the plurality of page buffers outputs the fail bit stored in its sense latch in response to a program verify signal during the program verify operation.

16. The method of claim 15, wherein the selected memory cells are flash memory cells.

17. A memory system comprising:

a nonvolatile memory device; and

a memory controller controlling the nonvolatile memory device to perform a program operation comprising applying a program pulse to selected memory cells, detecting a number of failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the detected number of failed program bits and disturbed inhibit bits,

wherein the disturbed inhibit bits include at least one disturbed inhibit bit among erase bits or at least one disturbed inhibit bit among passed program bits.

18. The memory system of claim 17, wherein the nonvolatile memory device and the memory controller are incorporated in a solid state drive.

19. The memory system of claim 17, wherein the memory controller controls the nonvolatile memory device to terminate the program operation upon determining that the detected number of failed program bits and disturbed inhibit bits exceeds a predetermined reference number.

20. The memory system of claim 17, further comprising:

an error correction code circuit configured to correct the failed program bits and disturbed inhibit bits in a read operation performed subsequent to the program operation.