Hybrid volatile and non-volatile memory device with a shared interface circuit

• US 8,427,891 B2
• Filed: 04/17/2008
• Issued: 04/23/2013
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C.
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US12/596,115
• Publication Number:
  US 20100110748A1
• Time in Patent Office: 1,832 Days
• Field of Search: 365/51, 365/63, 365/185.08, 365/185.05, 365/189.2, 365/189.17, 365/189.07
• US Class Current: 365/189.2
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.

Claims

1. A memory device disposed within an integrated circuit (IC) package and comprising:

a first storage die having an array of volatile storage cells;

a second storage die having an array of non-volatile storage cells;

a shared interface circuit coupled to the first storage die and the second storage die to receive information associated with a memory access operation to be performed within the memory device, the information specifying an access to either the first or the second storage die, the shared interface circuit including selection circuitry responsive to the information to select, according to the information, either the first storage die or the second storage die to be accessed in the memory access operation.

2. The memory device of claim 1 wherein the information associated with the memory access operation comprises an address value, and wherein the shared interface circuit comprises a circuit to select, according to one or more bits of the address value, either the first storage die or the second storage die to be accessed in the memory access operation.

3. The memory device of claim 1 wherein the information associated with the memory access operation comprises a memory access command that indicates the memory access operation to be performed and which of the first and second storage dice is to be accessed in the memory access operation, and wherein the shared interface circuit comprises a circuit to select, according to one or more bits of the memory access command, either the first storage die or the second storage die to be accessed in the memory access operation.

4. The memory device of claim 1 wherein the shared interface circuitry comprises circuitry to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice in response to the memory access commands.

5. The memory device of claim 1 wherein the shared interface circuit is disposed within the IC package on a third die.

6. The memory device of claim 1 wherein the shared interface circuit is formed at least in part on at least one of the first and second storage dice.

7. The memory device of claim 1 wherein the first storage die is a dynamic random access memory (DRAM) die comprising an array of DRAM cells.

8. The memory device of claim 1 wherein the first storage die is a static random access memory (SRAM) die comprising an array of SRAM cells.

9. The memory device of claim 1 wherein the second storage die is a Flash memory die comprising an array of Flash memory cells.

10. The memory device of claim 1 further comprising a programmable register to indicate a range of address values that are common between the array of volatile storage cells and the array of non-volatile storage cells.

11. The memory device of claim 1 wherein the information associated with the memory access operation comprises an input address value, and wherein the shared interface circuit comprises a comparator circuit to compare the input address value with an address value that indicates a start address within either the first storage die or the second storage die.

12. The memory device of claim 11 wherein the comparator circuit generates a comparison result that indicates whether the input address value falls within an address range of the first storage die or an address range of the second storage die.

13. The memory device of claim 12 wherein the memory access operation is carried out within the first storage die if the comparison result indicates that the input address value falls within the address range of the first storage die, and within the second storage die if the comparison result indicates that the input address value falls within the address range of the second storage die.

14. A method of accessing storage locations within an integrated circuit (IC) device, the method comprising:

receiving, within a shared interface of the IC device, information that specifies a memory access to be performed within either a first IC storage die having an array of volatile storage cells or a second IC storage die having an array of non-volatile storage cells;

selecting either the first IC storage die or the second IC storage die via selection circuitry based on the information; and

performing the memory access within either the first IC storage die or the second IC storage die according to the information.

15. The method of claim 14 wherein the information comprises an address value, and wherein performing the memory access within either the first IC storage die or the second IC storage die according to the information comprises performing the memory access within either the first IC storage die or the second IC storage die according to one or more bits within the address value.

16. The method of claim 15 wherein performing the memory access within either the first IC storage die or the second IC storage die according to one or more bits within the address value comprises performing the memory access within either the first IC storage die or the second IC storage die according to whether the address value falls within an address range of the first IC storage die or an address range of the second IC storage die.

17. The method of claim 14 wherein the information comprises a memory access command that indicates which of the first and second storage dice is to be accessed in a memory access operation and wherein performing the memory access within either the first IC storage die or the second IC storage die according to the information comprises performing the memory access within either the first IC storage die or the second IC storage die according to one or more bits within the memory access command.

18. The method of claim 14 wherein the first IC storage die is a dynamic random access memory (DRAM) die comprising an array of DRAM memory cells.

19. The method of claim 14 wherein the second IC storage die is a Flash memory die comprising an array of Flash memory cells.

20. A memory device comprising:

a first storage die having an array of volatile storage cells;

a second storage die having an array of non-volatile storage cells;

means for receiving, within a shared interface of the memory device, information that specifies a memory access to be performed within either the first storage die or the second storage die;

means for selecting either the first storage die or the second storage die based on the information; and

means for performing the memory access within either the first storage die or the second storage die according to the information.

21. Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit memory device, the information including descriptions of:

a first storage die having an array of volatile storage cells;

a second storage die having an array of non-volatile storage cells;

a shared interface circuit to receive information associated with a memory access operation to be performed within the memory device, the information specifying an access to either the first or the second storage die, the shared interface circuit including selection circuitry responsive to the information and to select, according to the information, either the first storage die or the second storage die to be accessed in the memory access operation.