Memory with output control

• US 8,427,897 B2
• Filed: 05/03/2012
• Issued: 04/23/2013
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Oh, Hakjune, Pyeon, Hong Beom
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/463,339
• Publication Number:
  US 20120215974A1
• Time in Patent Office: 355 Days
• Field of Search: 365/185.11, 365/185.15, 365/185.12, 365/189.04, 365/189.05, 365/219, 365/221, 365/230.05, 365/230.08
• US Class Current: 365/221
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A memory device comprising:

flash memory;

a clock input configured to receive a clock signal;

a common command and data input configured to receive input data and command data at different times;

a first control input configured to receive a first of two control signals;

a second control input configured to receive a second of the two control signals;

core circuitry configured to execute an operation on the flash memory corresponding to the command data; and

latch circuitry configured to;

latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input, and

latch the input data in synchronization with both rising and falling edges of the clock signal.

2. The memory device as claimed in claim 1 wherein only the first of the two control signals is held at the active logic level for at least the duration of time that the command data is received at the common command and data input.

3. The memory device as claimed in claim 1 wherein the first of the two control signals is an input port enable signal.

4. The memory device as claimed in claim 1 wherein the second of the two control signals is an output port enable signal.

5. The memory device as claimed in claim 1 wherein the operation is an erase operation.

6. The memory device as claimed in claim 1 wherein the operation is a program operation.

7. The memory device as claimed in claim 1 wherein the common command and data input is a serial input.

8. The memory device as claimed in claim 3 wherein the flash memory is NAND flash memory.

9. The memory device as claimed in claim 1 wherein a transitioning of the first of the two control signals from an inactive state to the active state indicates a beginning of the command data being received at the common command and data input.

10. A system comprising:

a controller; and

a memory device according to claim 1, the memory device being communicatively coupled to the controller.

11. A method carried out in a memory device having flash memory and a common command and data input, the method comprising:

receiving a clock signal;

receiving, at the common command and data input and at different times, input data and command data;

receiving a first of two control signals;

receiving a second of the two control signals;

latching the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input;

latching the input data in synchronization with both rising and falling edges of the clock signal; and

executing an operation on the flash memory corresponding to the command data.

12. The method as claimed in claim 11 wherein only the first of the two control signals is held at the active logic level for at least the duration of time that the command data is received at the common command and data input.

13. The method as claimed in claim 11 wherein the first of the two control signals is an input port enable signal.

14. The method as claimed in claim 11 wherein the second of the two control signals is an output port enable signal.

15. The method as claimed in claim 11 wherein the operation is an erase operation.

16. The method as claimed in claim 11 wherein the operation is a program operation.

17. The method as claimed in claim 11 wherein the common command and data input is a serial input.

18. The method as claimed in claim 11 wherein the flash memory is NAND flash memory.

19. The method as claimed in claim 11 wherein a transitioning of the first of the two control signals from an inactive state to the active state indicates a beginning of the command data being received at the common command and data input.