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Memory with output control

  • US 8,427,897 B2
  • Filed: 05/03/2012
  • Issued: 04/23/2013
  • Est. Priority Date: 09/30/2005
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • flash memory;

    a clock input configured to receive a clock signal;

    a common command and data input configured to receive input data and command data at different times;

    a first control input configured to receive a first of two control signals;

    a second control input configured to receive a second of the two control signals;

    core circuitry configured to execute an operation on the flash memory corresponding to the command data; and

    latch circuitry configured to;

    latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input, andlatch the input data in synchronization with both rising and falling edges of the clock signal.

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