Economical, RF transparent, selective code phased array antenna processor

• US 8,428,105 B2
• Filed: 08/07/2009
• Issued: 04/23/2013
• Est. Priority Date: 08/07/2009
• Status: Expired due to Fees

• Current Assignee: The Renda Trust
• Original Assignee: The Renda Trust
• Inventors: Wang, James, Marringa, Menno
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): PANWALKAR, VINEETA S
• Application Number:
  US12/537,258
• Publication Number:
  US 20110032972A1
• Time in Patent Office: 1,355 Days
• Field of Search: 375140-152, 375/242, 375/243, 375/354, 375/362, 375/367, 375/267, 375/299, 455/130, 455/150.1, 455/196.1, 455/193.1, 341/126, 341/155, 341/172
• US Class Current: 375/141
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 7/0617 for beam forming
• CPC Class Codes: H04B 7/086 using weights depending on external parameters, e.g. direction of arrival [DOA], predetermined weights or beamforming
• CPC Class Codes: H04B 7/0897 using beamforming per multi-path, e.g. to cope with different directions of arrival [DOA] at different multi-paths
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A single chip diversity beamforming antenna array processor is disclosed. The processor utilizes low-power and low area circuits to achieve combining gain mitigate the effects of multipath fading, provide spatial suppression, and provide diversity gain to a single input receiver. The device is radiofrequency transparent yet provides antenna gain by selective three G and four G code acquisition and tracking of a desired downlink channel.

Claims

1. A solid-state device comprising the following circuits:

a plurality of adaptive amplifier modulator circuits;

at least one radiofrequency digitizer circuit;

a USB engine and microcode power selector interface;

a PN code selective beamforming engine circuit; and

a many input single output radio frequency (RF) combiner circuit,

wherein the PN code selective beamforming engine circuit comprises;

a plurality of de-spreader circuits, a weight phasor angle circuit, a reference signal circuit, and a weight magnitude normalization circuit, the weight magnitude normalization circuit coupled to the adaptive amplifier modulator circuit, the reference signal circuit coupled to the weight magnitude normalization circuit and further coupled to the weight phasor angle circuit, and the plurality of de-spreader circuits, the weight phasor angle circuit coupled to the reference signal circuit and to the plurality of de-spreader circuits, and each de-spreader circuit further coupled to the at least one radiofrequency digitizer circuit by an amplitude input and a phase input and to the USB engine and microcode power selector interface.

2. The solid-state device of claim 1 wherein each adaptive amplifier modulator circuit comprises a low noise amplifier circuit, and a modulator circuit, the modulator circuit coupled to a radiofrequency output and the PN code selective beamforming engine circuit whereby the radiofrequency output is controlled by a plurality of weights, a radiofrequency input coupled to the low noise amplifier, and the at least one radiofrequency digitizer circuit coupled to the output of the low noise amplifier circuit.

3. The solid-state device of claim 1 wherein one of the plurality of adaptive amplifier modulator circuits comprises an integrated low noise amplifier modulator circuit;

the integrated low noise amplifier modulator circuit coupled to a radiofrequency output and the PN code selective beamforming engine circuit whereby the radiofrequency output is controlled by a plurality of weights, a radiofrequency input coupled to the integrated low noise amplifier modulator circuit, and the at least one radiofrequency digitizer circuit coupled to the output of the integrated low noise amplifier modulator circuit.

4. The solid-state device of claim 1 wherein the adaptive amplifier modulator circuit further comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.

5. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises:

a buffer, a sampler, a sampling oscillator, a switched capacitor analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor analog filter coupled between the digitizer and the sampler, the sampler further coupled between the sampling oscillator and the buffer and the buffer further coupled to the circuit input.

6. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises:

a buffer, a sampler, an adjustable frequency sampling oscillator, a switched capacitor analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor analog filter coupled between the digitizer and the sampler, the sampler further coupled between the adjustable frequency sampling oscillator and the buffer and the buffer further coupled to the circuit input.

7. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises:

a buffer, a sampler, a sampling oscillator, a switched capacitor tunable analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor tunable analog filter coupled between the digitizer and the sampler, the sampler further coupled between the sampling oscillator and the buffer and the buffer further coupled to the circuit input.

8. The solid-state device of claim 5 wherein the sampling oscillator comprises a direct digital synthesizer driven by an on-chip oscillator and an external crystal to provide an adjustable frequency for under sampling a radiofrequency signal down and selecting the desired channel to pass through a channel filter.

9. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit further comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.

10. The device of claim 1 wherein each of the plurality of de-spreader circuits comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.

11. The device of claim 1 wherein each of the plurality of de-spreader circuits comprises:

a pair of inputs I and Q, a pair of digital multipliers, a pair of low pass filters, a code generator and acquisition and tracking circuit and a scale factor circuit, the scale factor circuit coupled to a circuit output and coupled to both inputs and both low pass filters, each digital multiplier coupled to a circuit input and to a low pass filter, the code generator and acquisition and tracking circuit coupled to an input and to each digital multiplier, and each low pass filter further coupled to a circuit output selected I and selected Q.

12. The de-spreader circuit of claim 11 wherein the code generator acquisition and tracking circuit is adapted to track a common pilot channel.

13. The de-spreader circuit of claim 11 wherein the code generator acquisition and tracking circuit is adapted to track a synchronization channel.

14. A solid-state device comprising the following circuits:

a plurality of adaptive amplifier modulator circuits;

at least one radiofrequency digitizer circuit;

a modem baseband processor and microcode power selector interface;

a PN code selective beamforming engine circuit; and

a many input single output radio frequency (RF) combiner circuit,

wherein the PN code selective beamforming engine circuit comprises;

a plurality of de-spreader circuits, a weight phasor angle circuit, a reference signal circuit, and a weight magnitude normalization circuit, the weight magnitude normalization circuit coupled to the adaptive amplifier modulator circuit, the reference signal circuit coupled to the weight magnitude normalization circuit and further coupled to the weight phasor angle circuit, and the plurality of de-spreader circuits, the weight phasor angle circuit coupled to the reference signal circuit and to the plurality of de-spreader circuits, and each de-spreader circuit further coupled to the at least one radiofrequency digitizer circuit by an amplitude input and a phase input and to the USB engine and microcode power selector interface.

15. The device of claim 14 coupled to a multiple input multiple output modem configured in spatial multiplexing operational mode.

16. The device of claim 14 coupled to a multiple input multiple output modem configured in diversity combining operational mode.

17. The device of claim 14 coupled to a transmit path in a time-division duplexing system to produce a transmit phased array system.