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Economical, RF transparent, selective code phased array antenna processor

  • US 8,428,105 B2
  • Filed: 08/07/2009
  • Issued: 04/23/2013
  • Est. Priority Date: 08/07/2009
  • Status: Expired due to Fees
First Claim
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1. A solid-state device comprising the following circuits:

  • a plurality of adaptive amplifier modulator circuits;

    at least one radiofrequency digitizer circuit;

    a USB engine and microcode power selector interface;

    a PN code selective beamforming engine circuit; and

    a many input single output radio frequency (RF) combiner circuit,wherein the PN code selective beamforming engine circuit comprises;

    a plurality of de-spreader circuits, a weight phasor angle circuit, a reference signal circuit, and a weight magnitude normalization circuit, the weight magnitude normalization circuit coupled to the adaptive amplifier modulator circuit, the reference signal circuit coupled to the weight magnitude normalization circuit and further coupled to the weight phasor angle circuit, and the plurality of de-spreader circuits, the weight phasor angle circuit coupled to the reference signal circuit and to the plurality of de-spreader circuits, and each de-spreader circuit further coupled to the at least one radiofrequency digitizer circuit by an amplitude input and a phase input and to the USB engine and microcode power selector interface.

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