Serial interface NAND

• US 8,429,329 B2
• Filed: 10/17/2007
• Issued: 04/23/2013
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Radmax Power LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T., Yu, Jeff
• Primary Examiner(s): RUTZ, JARED IAN
• Application Number:
  US11/873,816
• Publication Number:
  US 20090103364A1
• Time in Patent Office: 2,015 Days
• Field of Search: 711/118, 711/115, 711/165, 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence

Abstract

Embodiments are provided that include operating a NAND memory device via an SPI interface. One such method includes cache loading a NAND memory device including loading data into a cache of the NAND memory device, writing data from the cache of the NAND memory device to an address of a memory array of the NAND memory device, and polling to determine the status of the data being written. Further one such method includes caching of data in a NAND memory device via an SPI interface comprising loading first data to a cache of the NAND memory device, writing the first data to a first address of a NAND memory array of the NAND memory device, polling the status of the cache, if polling indicates that the cache is ready, then loading a portion of the cache with second data, polling the status of the cache and the NAND memory device, and if polling indicates that the cache is ready and the device is ready, writing the second data to a second address of the NAND memory array of the NAND memory device.

Claims

1. A method of cache loading a NAND memory device via an SPI interface comprising:

loading data into a specified address of a cache of the NAND memory device, wherein the specified address of the cache of the NAND memory device is specified by a first program sequence sent to the SPI interface from a host external to the NAND memory device;

writing data from the specified address of the cache of the NAND memory device to a specified address of a memory array of the NAND memory device, wherein the specified address of the memory array of the NAND memory device is specified by a second program sequence sent to the SPI interface from the host; and

polling to determine the status of the data being written.

2. The method of claim 1, wherein loading data into the address of the cache of the NAND memory device comprises issuing the first program sequence, wherein the first program sequence comprises a program load sequence to the SPI interface to load data into the cache.

3. The method of claim 2, wherein the program load sequence comprises a 1 byte command, a 2 byte column address corresponding to the address of the cache, and at least 1 data byte.

4. The method of claim 1, wherein writing data from the cache of the NAND memory device to an address of the memory array of the NAND memory device comprises issuing the second program sequence, wherein the second program sequence comprises a program execute sequence to the SPI interface to write data to the address of the NAND memory device.

5. The method of claim 1, comprising executing error correction code when a chip select signal is driven to a disabled state.

6. The method of claim 1, wherein polling to determine the status of the data being written comprises issuing a read status command to the SPI interface to poll the status of the data written to the address of the NAND memory device.

7. A method of inputting data to a NAND memory device comprising:

issuing a program load random data input sequence from a host to an SPI controller to load new data into one of a plurality of column addresses of a cache of a NAND memory device without initializing data stored at nearby column addresses of the cache, wherein the program load random data input sequence specifies the one of the plurality of column addresses of the cache; and

issuing a program execute sequence from the host to the SPI controller to load data stored in the cache at or near the one of the plurality of column addresses of the cache to a specified address of a NAND memory array of the NAND memory device, wherein the program execute sequence specifies the specified address of the NAND memory array, wherein the data stored in the cache at or near the one of the plurality of column addresses of the cache comprises the new data.

8. The method of claim 7, wherein the program load random data input sequence comprises a 1 byte command, a 12 bit column address, and at least 1 data byte.

9. The method of claim 7, wherein the program load random data input sequence comprises a dummy bit to align the address to a byte format.

10. A method of moving data within a NAND memory device comprising:

communicating via an SPI bus to an SPI controller from a host, wherein communicating comprises generating a first sequence to read data from a first address of a NAND memory array of the NAND memory device into a specified cache address of the NAND memory device, wherein the first sequence specifies the specified cache address, and generating a second sequence to write the data from the specified cache address of the NAND memory device to a second address of the NAND memory array of the NAND memory device, wherein the second sequence specifies the second address of the NAND memory array.

11. The method of claim 10, wherein the first sequence comprises a page read command and the second sequence comprises a program execute command.

12. The method of claim 10, comprising polling a status of the data written to the NAND memory array of the NAND memory device.

13. The method of claim 10, comprising generating a read status command to poll a status of the data written to the second address of the NAND memory array of the NAND memory device.

14. The method of claim 10, wherein moving the data within the NAND memory device is employed based on a wear-leveling algorithm.

15. A method of modifying internal data in a NAND memory device comprising:

issuing a page read sequence from a host to an SPI controller to read data from a first address of a memory array of the NAND memory device and load the data into a specified cache address of the NAND memory device, wherein the page read sequence specifies the specified cache address of the NAND memory device;

issuing a program load random data input sequence from the host to the SPI controller to load new data into one of a plurality of column addresses associated with the specified cache address of the NAND memory device, wherein the program load random data input sequence specifies the one of the plurality of column addresses; and

issuing a program execute sequence from the host to the SPI controller to write data from the specified cache address of the NAND memory device to a second address of the memory array of the NAND memory device, wherein the program execute sequence specifies the second address of the memory array of the NAND memory device.

16. The method of claim 15, comprising executing error correction code before and after issuing the program load random data input sequence.

17. The method if claim 15, wherein the program load random data input sequence only modifies the data overwritten by the new data.

18. The method of claim 15, comprising moving the data between the first address and second address of the memory array of the NAND memory device based on a wear leveling algorithm.

19. A method of caching data in a NAND memory device via an SPI interface comprising:

loading first data to a specified cache address of the NAND memory device by issuing a first program load sequence that specifies the specified cache address to an SPI controller from a host;

writing the first data from the specified cache address to a first address of a NAND memory array of the NAND memory device by issuing a first program execute sequence that specifies the first address of the NAND memory device to the SPI controller from the host;

polling a status of the cache by issuing a first read status sequence to the SPI controller;

if polling indicates that the cache is ready, then loading a portion of the specified cache address with second data by issuing a second program load sequence that specifies at least the portion of the specified cache address to the SPI controller from the host;

polling the status of the cache and the NAND memory device by issuing a second read status sequence to the SPI controller; and

if polling indicates that the cache is ready and the device is ready, writing the second data from the specified cache address to a second address of the NAND memory array of the NAND memory device by issuing a second program execute sequence that specifies the second address of the NAND memory device to the SPI controller from the host.

20. The method of claim 19, wherein the method is repeated for additional sets of data to be written to the memory array of the NAND memory device.

21. The method of claim 19, wherein polling the status of the cache of the NAND memory device comprises the SPI controller outputting a status register byte that comprises a cache status bit.

22. The method of claim 19, wherein polling the status of the NAND memory device comprises the SPI controller outputting a status register byte that comprises a device status bit.

23. The method of claim 19, comprising polling the status of the cache and the NAND memory device to determine if writing the second data to a second address of the NAND memory array of the NAND memory device has completed.