Cache line use history based done bit modification to D-cache replacement scheme

• US 8,429,350 B2
• Filed: 02/27/2012
• Issued: 04/23/2013
• Est. Priority Date: 05/28/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Primary Examiner(s): Tran, Denise
• Application Number:
  US13/405,572
• Publication Number:
  US 20120159075A1
• Time in Patent Office: 421 Days
• Field of Search: None
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value

Abstract

A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times.

Claims

1. An integrated circuit device, comprising:

a processor core;

a level one (L1) cache;

a level two (L2) cache; and

a history count, kept for each cache line in the L1 cache, the history count for indicating a number of load references to data in the cache line a last time the cache line was called in to the L1 cache; and

a comparator configured to compare the history count to a reference count to determine when the reference count is equal to the history count, and a confirmation count that corresponds to reliability of an estimate that the cache line in the L1 cache is marked as least recently used, and when the history count equals the reference count, the confirmation count is incremented and an L1 extended cache directory and count flags is moved to an L2 extended cache directory.

2. The integrated circuit device of claim 1, further comprising a counter that counts each time the cache line is referenced in the L1cache.

3. The integrated circuit device of claim 2, wherein the counter updates a reference counter in the L2 cache each time the cache line is referenced in the L1 cache.

4. The integrated circuit device of claim 3, further comprising a loader that loads the cache line into a data line buffer for access by the processor if the history of access is equal to two.