Microprocessor apparatus and method for securing a programmable fuse array

• US 8,429,471 B2
• Filed: 06/25/2010
• Issued: 04/23/2013
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Jain, Dinesh K.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US12/823,345
• Publication Number:
  US 20110316613A1
• Time in Patent Office: 1,033 Days
• Field of Search: 327/525, 327/540, 326/8, 326/37, 714/726, 714/727, 714/742, 714/745
• US Class Current: 714/726
• CPC Class Codes: H01H 2085/0275 Structural association with a printed circuit board
• CPC Class Codes: H01H 85/0241 Structural association of a fuse and another component or apparatus switches with built-in fuses H01H9/10, spark-gap arresters H01H85/44, transformers and inductances H01F27/402, capacitors H01G2/14, lamps H01K1/66, semiconductors H01L23/5256 or H01L23/62

Abstract

An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indicates whether the extended JTAG features are to be disabled. The level sensor monitors an external voltage signal, and indicates that the external voltage signal is at a legal level. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. The blow controller receives a voltage, and blows a selected fuse within a fuse array responsive to a valve of the voltage.

Claims

1. An apparatus in an integrated circuit for precluding the use of extended JTAG operations, the apparatus comprising:

a JTAG control chain, configured to enable/disable the extended JTAG operations;

a feature fuse, configured to indicate whether the extended JTAG features are to be disabled;

a level sensor, configured to monitor an external voltage signal, and configured to indicate, that said external voltage signal is at a legal level;

an access controller, coupled to said feature fuse, said level sensor, and said JTAG control chain, configured to determine if said feature fuse is blown, and configured to direct said JTAG control chain to disable the extended JTAG operations if said feature fuse is blown, and configured to direct said JTAG control chain to disable the extended JTAG operations if said external voltage signal is at an illegal level regardless of whether said feature fuse is blown; and

a blow controller, coupled to a fuse array, configured to receive a voltage, and configured to blow a selected fuse within said fuse array responsive to a value of said voltage, wherein blowing of said selected fuse is allowed only when the extended JTAG operations are enabled.

2. The apparatus as recited in claim 1, wherein the extended JTAG operations comprise reading of fuse states within a fuse array.

3. The apparatus as recited in claim 1, wherein the extended JTAG operations comprise blowing of fuses within a fuse array.

4. The apparatus as recited in claim 1, wherein the extended JTAG operations comprise reading of microinstructions stored within a microcode storage element.

5. The apparatus as recited in claim 1, wherein said access controller receives a reset signal, and wherein said access controller determines if said feature fuse is blown following assertion of said reset signal.

6. The apparatus as recited in claim 1, wherein the integrated circuit comprises a microprocessor.

7. The apparatus as recited in claim 1, wherein only JTAG boundary scan and test operations are enabled when the extended JTAG operations are disabled.

8. An apparatus in an integrated circuit for precluding the use of extended JTAG operations, the apparatus comprising:

a microprocessor, comprising;

a JTAG control chain, configured to enable/disable the extended JTAG operations;

a feature fuse, configured to indicate whether the extended JTAG operations are to be disabled;

a level sensor, configured to monitor an external voltage signal, and configured to indicate that said external voltage signal is at a legal level;

an access controller, coupled to said feature fuse, said level sensor, and said JTAG control chain, configured to determine if said feature fuse is blown, and configured to direct said JTAG control chain to disable the extended JTAG operations if said feature fuse is blown, and configured to direct said JTAG control chain to disable the extended JTAG operations if said external voltage signal is at an illegal level regardless of whether said feature fuse is blown; and

a blow controller, coupled to a fuse array, configured to receive a voltage, and configured to blow a selected fuse within said fuse array responsive to a value of said voltage, wherein blowing of said selected fuse is allowed only when the extended JTAG operations are enabled.

9. The apparatus as recited in claim 8, wherein the extended JTAG operations comprise reading of fuse states within a fuse array.

10. The apparatus as recited in claim 8, wherein the extended JTAG operations comprise blowing of fuses within a fuse array.

11. The apparatus as recited in claim 8, wherein the extended JTAG operations comprise reading of microinstructions stored within a microcode storage element.

12. The apparatus as recited in claim 8, wherein said access controller receives a reset signal, and wherein said access controller determines if said feature fuse is blown following assertion of said reset signal.

13. The apparatus as recited in claim 8, wherein said microprocessor comprises an x86-compatible microprocessor.

14. The apparatus as recited in claim 8, wherein only JTAG boundary scan and test operations are enabled when the extended JTAG operations are disabled.

15. A method for precluding the use of extended JTAG operations in an integrated circuit, the method comprising:

via blowing a feature fuse that is disposed within the integrated circuit, indicating that extended JTAG operations are to be disabled;

first determining if the feature fuse is blown, and directing a JTAG control chain to disable the extended JTAG operations;

second determining if an external voltage signal is at a legal level;

disabling the extended JTAG operations if the feature fuse is blown, and directing the JTAG control chain to disable the extended JTAG operations if the external voltage is at an illegal level regardless of whether the feature fuse is blown; and

receiving a voltage, and blowing a selected fuse within a fuse array responsive to a value of the voltage, wherein said blowing is allowed only when the extended JTAG operations are enabled.

16. The method as recited in claim 15, wherein the extended JTAG operations comprise reading of fuse states within a fuse array.

17. The method as recited in claim 15, wherein the extended JTAG operations comprise blowing of fuses within a fuse array.

18. The method as recited in claim 15, wherein the extended JTAG operations comprise reading of microinstructions stored within a microcode storage element.

19. The method as recited in claim 15, wherein said first determining comprises:

receiving a reset signal, and performing said first determining following assertion of the reset signal.

20. The method as recited in claim 15, wherein the integrated circuit comprises a microprocessor.

21. The method as recited in claim 15, further comprising:

enabling only JTAG boundary scan and test when the extended JTAG operations are disabled.