Method and system for feed-forward advanced process control

• US 8,429,569 B2
• Filed: 04/14/2011
• Issued: 04/23/2013
• Est. Priority Date: 04/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chun-Hung, Turn, Li-Kong, Chang, Keh-Wen, Lin, Juin-Hung, Chung, Hsueh-Yi, Yu, Chih-Jen
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US13/086,935
• Publication Number:
  US 20120264063A1
• Time in Patent Office: 740 Days
• Field of Search: 716 50- 56, 430/5, 430/30
• US Class Current: 716/51
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70558 Dose control, i.e. achievement of a desired dose
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]

Abstract

A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.

Claims

1. A method, comprising:

providing a present wafer to be processed by a photolithography tool to form a new integrated circuit design thereon;

selecting a processed wafer out of a plurality of previously processed wafers, the processed wafer having a past integrated circuit design different than the new integrated circuit design, the selecting based upon the similarity of the past integrated circuit design to the new integrated circuit design;

selecting a plurality of critical dimension (CD) data points extracted from the processed wafer after the processed wafer was etched, wherein the selecting the plurality of CD data points includes;

selecting the plurality of CD data points from a plurality of fields on the processed wafer; and

selecting a subset of the plurality of CD data points, the subset including CD data points extracted from a plurality of fields on the processed wafer, wherein the selecting the subset includes;

grouping fields on the processed wafer into a plurality of groups;

randomly selecting a primary field from each of the plurality of groups; and

selecting a first number of CD data points from each of the primary fields and a second number of CD data points from each of the remaining fields on the wafer, the first number being greater than the second number;

creating an initial exposure dose map for the new integrated circuit design using the plurality of CD data points; and

controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new integrated circuit design on the present wafer.

2. The method of claim 1,

including modeling the plurality of CD data points with a function relating CD to position on the processed wafer;

creating a field layout on the present wafer for the new integrated circuit design; and

wherein the creating the initial exposure dose map includes using the function and the field layout to create the initial exposure dose map.

3. The method of claim 2, wherein the creating the initial exposure dose map includes:

calculating an average CD for the processed wafer using the function;

calculating an average CD for each field in the field layout using the function;

calculating a delta CD for each field;

calculating a dose adjustment for each field using the delta CD;

creating a baseline exposure dose map having the field layout; and

creating a refined exposure dose map by adding to each field of the baseline exposure dose map the respective dose adjustment.

4. The method of claim 3,

wherein the calculating the delta CD for each field includes calculating the difference between the average CD for each field and the average CD for the processed wafer;

and

wherein the calculating the dose adjustment for each field is based on data relating a change in dose to a change in CD.

5. The method of claim 1, wherein the selecting the processed wafer is further based on one or more of an amount of time since the processed wafer was processed and the process tools used to form the past integrated circuit design on the processed wafer.

6. The method of claim 1,

wherein the plurality of groups includes four groups;

and

wherein the first number of CD data points includes approximately sixty data points and the second number of CD data points includes approximately sixteen data points.

7. The method of claim 1, wherein the function is a polynomial function.

8. The method of claim 7, wherein the polynomial function is a Zernike polynomial function.

9. A method, comprising:

selecting a photolithography tool and an etching tool to be used in processing an unprocessed chip design;

selecting, from a database of historical processing data, a set of critical dimension (CD) data extracted from a wafer previously processed by the photolithography tool and the etching tool, the previously processed wafer having a chip design substantially similar to the unprocessed chip design;

selecting a subset of the set of the CD data, the subset including CD measurements from a plurality of fields on the previously processed wafer;

creating an inter-field model of the CD measurements with a polynomial function;

creating a field layout for the unprocessed chip design;

creating an exposure dose map to control the photolithography tool during a first cycle of a pilot run for the unprocessed chip design, the creating including;

creating a baseline exposure dose map with the field layout;

finding a dose adjustment for each field in the field layout using the inter-field model; and

updating each field of the baseline exposure dose map with the respective dose adjustment; and

patterning a present wafer with the unprocessed chip design using the photolithography tool and the etching tool, the photolithography tool being controlled by the exposure dose map.

10. The method of claim 9, wherein selecting the set of CD data is based in part on an amount of time since the previously processed wafer was processed by the photolithography tool.

11. The method of claim 9, wherein finding the dose adjustment for each field includes:

calculating an average CD for the previously processed wafer using the inter-field model;

calculating an average CD for each field in the field layout using the inter-field model;

calculating a delta CD for each field; and

calculating a dose adjustment for each field using the delta CD.

12. The method of claim 9, wherein the polynomial function is a Zernike polynomial function.

13. An advanced process control (APC) system for controlling a semiconductor processing tool, comprising:

a database operable to store historical data about processed wafers; and

a controller operable to control the semiconductor processing tool based on instructions stored in a non-transitory, computer-readable memory that;

select, from the historical data, a processed wafer with a past chip design out of a plurality of previously processed wafers based upon the similarity of the past chip design to a new chip design, the new chip design being different than the past chip design;

select a plurality of critical dimension (CD) data points extracted from the processed wafer after the processed wafer was etched;

model the plurality of CD data points with a polynomial function relating CD to position on the processed wafer;

create a field layout for the new chip design; and

create an initial exposure dose map for the new chip design using the function and the field layout, wherein the instructions that create the initial exposure dose map include instructions that;

calculate an average CD for the processed wafer using the function;

calculate an average CD for each field in the field layout using the function;

calculate a delta CD for each field;

calculate a dose adjustment for each field using the delta CD;

create a baseline exposure dose map having the field layout; and

create a refined exposure dose map by adding to each field of the baseline exposure dose map the respective dose adjustment.

14. The APC system of claim 13,

wherein the instructions that calculate the delta CD for each field include instructions that calculate a difference between the average CD for each field and the average CD for the processed wafer;

and

wherein the instructions that calculate the dose adjustment for each field do so based on data relating a change in dose to a change in CD.

15. The APC system of claim 13, wherein the instructions that select the processed wafer do so further based on one or more of an amount of time since the processed wafer was processed by the semiconductor processing tool and an identity of semiconductor processing tools used to process the processed wafer.

16. The APC system of claim 13, wherein the instructions that select the plurality of CD data points include instructions that:

select the plurality of CD data points from a plurality of fields on the processed wafer; and

select a subset of the plurality of CD data points, the subset including CD data points extracted from a plurality of fields on the processed wafer.

17. The APC system of claim 16, wherein the instructions that select a subset of data points include instructions that:

group fields on the processed wafer into a plurality of groups;

randomly select a primary field from each of the plurality of groups; and

select a first amount of data points from each of the primary fields and a second amount of data points from each of the remaining fields on the wafer, the first amount being greater than the second amount.