Three dimensional integrated circuits

• US 8,429,585 B2
• Filed: 02/27/2006
• Issued: 04/23/2013
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Lin, Sun
• Application Number:
  US11/363,304
• Publication Number:
  US 20060150137A1
• Time in Patent Office: 2,612 Days
• Field of Search: 716/12, 716/16, 716/121, 716/126, 716/128, 716/129, 716/130, 326 37- 50, 714/724, 714/725, 257/686
• US Class Current: 716/121
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

Claims

1. A semiconductor device, comprising:

a first module layer comprising a plurality of circuit blocks; and

a second module layer comprising a configuration circuit configured to program at least one of the circuit blocks, wherein the configuration circuit is dependent on at least one of the circuit blocks to access information from an external source,

wherein the first module layer and the second module layer form a stack.

2. The semiconductor device of claim 1, wherein the configuration circuit comprises a memory element.

3. The semiconductor device of claim 2, wherein the memory element comprises at least one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electromagnetic elements, carbon nano-tube elements, optical elements, mask programmable elements, and any other memory element.

4. The semiconductor device of claim 1, wherein the second module layer comprises at least one of a diode, a transistor, a capacitor, a resistor, an electrolyte, a refractive metal, a ferro-electric, a carbon nano-tube, a wire, a thin film element, a thin film resistor, a thin film capacitor, a thin film transistor (TFT), a magnetic element, a chemical element, and a photo-electric element.

5. The semiconductor device of claim 1, further comprising:

a third module layer comprising a routing circuit configured to electrically couple at least one of the circuit blocks to the configuration circuit,

wherein the first module layer, the second module layer, and the third module layer form the stack.

6. The semiconductor device of claim 1, wherein the configuration circuit comprises at least one of a first element coupled to a voltage source at a digital one voltage level and a second element coupled to a voltage source at a digital zero voltage level.

7. The semiconductor device of claim 6, wherein the first element comprises at least one of a thin-film P-type carrier transistor load and a resistor load.

8. The semiconductor device of claim 1, wherein the configuration circuit comprises at least one of a first programmable element coupled to a digital one supply voltage level and a second programmable element coupled to a digital zero supply voltage level.

9. The semiconductor device of claim 1, wherein a first circuit block of the circuit blocks includes a pass transistor, and wherein the configuration circuit is configured to provide a control signal to the pass transistor to configure the first circuit block to perform a function.

10. The semiconductor device of claim 1, wherein the first module layer comprises a semiconductor substrate layer.

11. A semiconductor device, comprising:

a first module layer comprising a circuit block including a transistor; and

a second module layer comprising a configuration circuit configured to program the circuit block, wherein the configuration circuit is configured to provide a signal to the transistor to configure the circuit block to perform a function, wherein the configuration circuit is dependent on the first module layer to access information from an external source,

wherein the first module layer and the second module layer form a stack.

12. The semiconductor device of claim 11, wherein the configuration circuit comprises a memory element.

13. The semiconductor device of claim 12, wherein the memory element comprises at least one of

a pull-up element coupled to a voltage source at digital one voltage level and

a pull-down element coupled to a voltage source at a digital zero voltage level,

wherein the configuration circuit is configured to provide a digital one signal by using the pull-up element, and

wherein the configuration circuit is configured to provide a digital zero signal by using the pull-down element.

14. The semiconductor device of claim 12, wherein the memory element comprises at least one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electrochemical elements, electromagnetic elements, carbon nano-tube elements, optical elements, mask programmable elements, and any other memory element.

15. The semiconductor device of claim 11, wherein the configuration circuit comprises a thin film transistor (TFT).

16. The semiconductor device of claim 15, wherein the thin film transistor (TFT) is coupled to a voltage source at a digital one voltage level.

17. The semiconductor device of claim 15, wherein the thin film transistor (TFT) is coupled to a voltage source at a digital zero voltage level.

18. The semiconductor device of claim 11, further comprising:

a third module layer comprising a routing circuit configured to electrically couple the circuit block to the configuration circuit,

wherein the first module layer, the second module layer, and the third module layer form the stack.

19. The semiconductor device of claim 11, wherein the configuration circuit comprises at least one of a first programmable element coupled to a digital one supply voltage level and a second programmable element coupled to a digital zero supply voltage level.

20. A semiconductor device, comprising:

a first module layer comprising a circuit block; and

a second module layer comprising a configuration circuit configured to program the circuit block,

wherein the configuration circuit is dependent on the first module layer to access information from an external source, and

wherein the first module layer and the second module layer form a stack.