Manufacturing method of semiconductor device

• US 8,431,449 B2
• Filed: 04/01/2011
• Issued: 04/30/2013
• Est. Priority Date: 04/09/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US13/078,021
• Publication Number:
  US 20110250724A1
• Time in Patent Office: 760 Days
• Field of Search: 438/104, 438/151, 438/161
• US Class Current: 438/161
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An embodiment is a manufacturing method of a semiconductor device including the steps of forming a first insulating film; forming a first mask over the first insulating film; performing a slimming process on the first mask to form a second mask; performing an etching process on the first insulating film using the second mask to form a second insulating film; forming a first conductive film covering the second insulating film; performing a polishing process on the first conductive film and the second insulating film to form a third insulating film, a source electrode, and a drain electrode having equal thicknesses; forming an oxide semiconductor film over the third insulating film, the source electrode, and the drain electrode; forming a gate insulating film over the oxide semiconductor film; and forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

Claims

1. A manufacturing method of a semiconductor device comprising the steps of:

forming a first insulating film over a substrate;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film by using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film and the substrate;

performing a polishing process on the first conductive film and the second insulating film, so that a third insulating film, a source electrode, and a drain electrode are formed;

forming an oxide semiconductor film over the third insulating film, the source electrode, and the drain electrode;

forming a gate insulating film over the oxide semiconductor film; and

forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

2. The manufacturing method of a semiconductor device according to claim 1, wherein the polishing process is performed so that the third insulating film, the source electrode, and the drain electrode have substantially equal thicknesses.

3. The manufacturing method of a semiconductor device according to claim 1, wherein a difference in height between a part of a surface of the third insulating film and a surface of the source electrode or a difference in height between a part of a surface of the third insulating film and a surface of the drain electrode is less than 5 nm.

4. The manufacturing method of a semiconductor device according to claim 1, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

5. The manufacturing method of a semiconductor device according to claim 1, wherein the first insulating film is formed on a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

6. The manufacturing method of a semiconductor device according to claim 1, wherein the slimming process is performed using an ashing process using an oxygen radical.

7. The manufacturing method of a semiconductor device according to claim 1, wherein the polishing process is performed using chemical mechanical polishing.

8. The manufacturing method of a semiconductor device according to claim 1, wherein the first insulating film is formed by sputtering.

9. A manufacturing method of a semiconductor device comprising the steps of:

forming a first transistor including a channel formation region, a first gate electrode over the channel formation region with a first gate insulating film located between the channel formation region and the first gate electrode, and a first source electrode and a first drain electrode which are electrically connected to the channel formation region;

forming an interlayer insulating film over the first transistor;

forming a first insulating film over the interlayer insulating film;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film by using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film and the interlayer insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a third insulating film, a second source electrode, and a second drain electrode are formed;

forming an oxide semiconductor film over the third insulating film, the second source electrode, and the second drain electrode;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the third insulating film.

10. The manufacturing method of a semiconductor device according to claim 9, wherein the polishing process is performed so that the third insulating film, the second source electrode, and the second drain electrode have substantially equal thicknesses.

11. The manufacturing method of a semiconductor device according to claim 9, wherein a difference in height between a part of a surface of the third insulating film and a surface of the second source electrode or a difference in height between a part of a surface of the third insulating film and a surface of the second drain electrode is less than 5 nm.

12. The manufacturing method of a semiconductor device according to claim 9, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

13. The manufacturing method of a semiconductor device according to claim 9, wherein the interlayer insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

14. The manufacturing method of a semiconductor device according to claim 9, wherein the slimming process is performed using an ashing process using an oxygen radical.

15. The manufacturing method of a semiconductor device according to claim 9, wherein the polishing process is performed using chemical mechanical polishing.

16. The manufacturing method of a semiconductor device according to claim 9, wherein the first insulating film is formed by sputtering.

17. A manufacturing method of a semiconductor device comprising the steps of:

forming a first gate electrode of a first transistor;

forming a first insulating film over the first gate electrode;

performing a first polishing process on the first insulating film;

forming a second insulating film over the first insulating film and the first gate electrode

forming a first mask over the second insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the second insulating film by using the second mask, so that a third insulating film is formed;

forming a first conductive film over the third insulating film and the first insulating film;

performing a second polishing process on the first conductive film and the third insulating film, so that an electrode electrically connected to the first gate electrode and a fourth insulating film are formed;

forming an oxide semiconductor film over and in contact with the electrode and the fourth insulating film;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the fourth insulating film.

18. The manufacturing method of a semiconductor device according to claim 17, wherein the second polishing process is performed so that the fourth insulating film and the electrode have substantially equal thicknesses.

19. The manufacturing method of a semiconductor device according to claim 17, wherein a difference in height between a part of a surface of the fourth insulating film and a surface of the electrode is less than 5 nm.

20. The manufacturing method of a semiconductor device according to claim 17, wherein the fourth insulating film has a thickness substantially equal to a thickness of the third insulating film.

21. The manufacturing method of a semiconductor device according to claim 17, wherein the second insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

22. The manufacturing method of a semiconductor device according to claim 17, wherein the slimming process is performed using an ashing process using an oxygen radical.

23. The manufacturing method of a semiconductor device according to claim 17, wherein the second polishing process is performed using chemical mechanical polishing.

24. The manufacturing method of a semiconductor device according to claim 17, wherein the second insulating film is formed by sputtering.