Method for fabricating a shielded gate trench MOS with improved source pickup layout
First Claim
1. A method for fabricating a semiconductor device, comprising:
- a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches;
a′
) forming asymmetric sidewalls in the gate runner/termination trenches, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered due to application of the second mask;
b) forming a first conductive region in the plurality of trenches;
c) forming an intermediate dielectric region and a termination protection region by applying a second mask;
d) forming a second conductive region in at least some of the trenches;
e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask;
f) disposing a metal layer; and
g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.
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Accused Products
Abstract
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
70 Citations
23 Claims
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1. A method for fabricating a semiconductor device, comprising:
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a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches; a′
) forming asymmetric sidewalls in the gate runner/termination trenches, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered due to application of the second mask;b) forming a first conductive region in the plurality of trenches; c) forming an intermediate dielectric region and a termination protection region by applying a second mask; d) forming a second conductive region in at least some of the trenches; e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask; f) disposing a metal layer; and g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask. - View Dependent Claims (2, 6, 7, 8, 9, 10, 11)
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3. A method for fabricating a semiconductor device, comprising:
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a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches; b) forming a first conductive region in the plurality of trenches; c) forming an intermediate dielectric region and a termination protection region by applying a second mask, wherein during formation of the intermediate dielectric region and the termination protection region, the second mask covers the gate runner/termination trenches and the source pickup trenches; d) forming a second conductive region in at least some of the trenches; e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask; f) disposing a metal layer; and g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask. - View Dependent Claims (4, 12, 13, 14, 15, 16, 17)
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5. A method for fabricating a semiconductor device, comprising:
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a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches, a′
) forming a plurality of trench spacers around openings of the plurality of trenches, wherein said trench spacers protect a semiconductor mesa area for forming a self-aligned cell contact;b) forming a first conductive region in the plurality of trenches; c) forming an intermediate dielectric region and a termination protection region by applying a second mask; d) forming a second conductive region in at least some of the trenches, wherein said trench spacers help protect a semiconductor surface while forming a polycide on the second conductive region; e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask; f) disposing a metal layer; and g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification