Semiconductor wafer, semiconductor device, and method of manufacturing a semiconductor device

• US 8,431,459 B2
• Filed: 03/26/2009
• Issued: 04/30/2013
• Est. Priority Date: 03/26/2008
• Status: Expired due to Fees

• Current Assignee: Sumitomo Chemical Company Limited, University of Tokyo
• Original Assignee: University of Tokyo
• Inventors: Takenaka, Mitsuru, Takagi, Shinichi, Hata, Masahiko, Ichikawa, Osamu
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/934,233
• Publication Number:
  US 20110018033A1
• Time in Patent Office: 1,496 Days
• Field of Search: 438/285, 438/586, 438/22
• US Class Current: 438/285
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.

Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

preparing a semiconductor wafer including (i) a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP and (ii) a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP;

forming an oxide layer by selectively oxidizing the second semiconductor layer relative to the first semiconductor layer; and

forming a control electrode above the oxide layer.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising:

after preparing the semiconductor wafer, forming an ohmic layer that covers the second semiconductor layer; and

forming an open portion in the ohmic layer to expose the second semiconductor layer at a bottom of the open portion, wherein

forming the oxide layer includes selectively forming the oxide layer in the open portion by oxidizing the second semiconductor layer exposed in the open portion.

3. The method of manufacturing a semiconductor device according to claim 2, wherein forming the oxide layer includes exposing, in an oxidation atmosphere, the second semiconductor layer exposed by the open portion with the ohmic layer as a mask to form the oxide layer in a self-aligning manner with the mask.

4. The method of manufacturing a semiconductor device according to claim 2, wherein the ohmic layer is a p-type or n-type group 3-5 compound semiconductor layer that does not contain aluminum and that lattice matches or pseudo-lattice matches with InP.

5. The method of manufacturing a semiconductor device according to claim 1, wherein forming the oxide layer includes using wet oxidation to form the oxide layer.