Shielded gate trench (SGT) MOSFET devices and manufacturing processes

• US 8,431,989 B2
• Filed: 04/28/2011
• Issued: 04/30/2013
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Lui, Sik K.
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US13/066,947
• Publication Number:
  US 20110204440A1
• Time in Patent Office: 733 Days
• Field of Search: 257330-334, 257/E29.201, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

Claims

1. A semiconductor power device comprising a plurality of power transistor cells surrounded by a trench opened in an active area on a semiconductor substrate wherein:

at least one of said cells constituting an active cell having a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding said cell wherein said trenched gate further having a bottom-shielding electrode filled with a gate material disposed below and insulated from said trenched gate; and

said bottom-shielding electrode filled with said gate material having a stepwise tapered profile having a stepwise reduced width and a substantially equal step height toward a bottom of said trench with a lining layer surrounded said gate material having a correspondingly stepwise increased thickness.

2. The semiconductor power device of claim 1 wherein:

at least one of said cells constituting a source contacting cell surrounded by said trench with a portion functioning as a source connecting trench filled with said gate material for electrically connecting between said bottom-shielding electrode and a source metal disposed directly on top of said source contact trench.

3. The trenched power semiconductor power device of claim 2 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a plurality of source openings opened through the insulation protective layer on top of said source region and said source connecting trench provided for electrically connecting the source region and the source connecting trench to said source metal disposed on top of the insulation protective layer.

4. The semiconductor power device of claim 2 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a gate opening opened through the insulation protective layer provided for electrically connecting the trenched gate to said gate pad disposed on top of the insulation protective layer.

5. The semiconductor power device of claim 4 wherein:

said gate opening is opened through the insulation protective layer directly above a gate runner trench in a termination area of said semiconductor power device.

6. The semiconductor power device of claim 5 wherein

said gate runner trench in the termination area is wider and deeper than said trench surrounding the transistor cells with said trenched gate disposed therein.

7. The semiconductor power device of claim 5 wherein:

said gate runner trench further includes SGT structure with said bottom-shielding electrode.

8. The semiconductor power device of claim 1 further comprising:

a deep body-dopant region in a termination area to function as a guard ring or Junction-termination extension type termination.

9. The semiconductor power device of claim 8 wherein:

said deep body-dopant region is deeper than and encompassing said gate runner trench in said termination area.

10. The semiconductor power device of claim 1 further comprising:

a drain electrode disposed on a bottom surface of said semiconductor substrate.

11. The semiconductor power device of claim 1 wherein:

each of said cells further includes a body region disposed between said trench surrounding said cells.

12. The semiconductor power device of claim 1 wherein

each of said cells further includes a body region disposed between said trench surrounding said cells wherein said body region in said active cell encompassing said source region disposed next to said trenched gate.

13. The semiconductor power device of claim 1 wherein:

an oxide layer is disposed above said bottom-shielding electrode to shield and insulate said bottom-shielding electrode from said trenched gate.

14. The semiconductor power device of claim 1 wherein:

an oxide layer is disposed above said bottom-shielding electrode to shield and insulate said bottom-shielding electrode from said trenched gate wherein said oxide layer above said bottom-shielding electrode is disposed in said trench with a predefined depth controlled by a timed etch process.

15. The semiconductor power device of claim 14 wherein:

said semiconductor power device having a reduced gate to drain capacitance Cgd depending on a depth of said oxide layer above said bottom-shielding electrode.

16. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising trenched metal oxide semiconductor field effect transistor (MOSFET) cells.

17. The semiconductor power device of claim 1 where:

said bottom-shielding electrode having at least two stepwise reduced widths and substantially equal step height toward a bottom of said trench with a lining layer surrounded said gate material having at least two correspondingly gradually stepwise increased thicknesses.

18. A semiconductor power device comprising:

a trenched gate having a bottom-shielding electrode filled with a gate material disposed below and insulated from a trenched gate wherein said bottom-shielding electrode filled with said gate material having a stepwise tapered profile having a stepwise reduced width and a substantially equal step height toward a bottom of said trench with a lining layer surrounded said gate material having a correspondingly gradually stepwise increased thickness.

19. The semiconductor power device of claim 18 where:

said bottom-shielding electrode having at least two stepwise reduced widths and substantially equal step height toward a bottom of said trench with a lining layer surrounded said gate material having at least two correspondingly gradually stepwise increased thicknesses.