Memory element and semiconductor device and method for manufacturing the same

• US 8,431,997 B2
• Filed: 09/13/2012
• Issued: 04/30/2013
• Est. Priority Date: 02/26/2007
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hirakata, Yoshiharu
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US13/614,560
• Publication Number:
  US 20130010534A1
• Time in Patent Office: 229 Days
• Field of Search: 257/350, 257/E21.477, 438/593, 365/151
• US Class Current: 257/350
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition

Abstract

It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.

Claims

1. A memory element comprising:

a first conductive layer over a first region of an insulating surface;

a second conductive layer over a second region of the insulating surface;

an insulating film between the insulating surface and the second conductive layer while the first conductive layer is in direct contact with the insulating surface; and

a first conductive particle between the first conductive layer and the second conductive layer, the first conductive particle having a surface covered with an organic film,

wherein the first region is apart from the second region, and

wherein the first and second conductive layers are electrically connectable to each other at least through the first conductive particle as a result in a writing operation of the memory element.

2. A memory element according to claim 1, further comprising at least one conductive particle between a side face of the first conductive layer and a side face of the second conductive layer which is opposite to the side face of the first conductive layer.

3. A memory element according to claim 1,

wherein a side face of the first conductive layer and a side face of the second conductive layer which is opposite to the side face of the first conductive layer have a tapered shape.

4. A memory element according to claim 1,

wherein the first conductive particle is a conductive fine particle having a grain size of greater than or equal to 5 nm and lass than or equal to 30 nm.

5. A memory element according to claim 1,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

6. A memory element according to claim 1,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line.

11. A memory element according to claim 1,

wherein the writing operation is performed by applying voltage between the first conductive layer and the second conductive layer.

12. A memory element according to claim 1, further comprising a second conductive particle over the second conductive layer.

13. A memory element according to claim 1, further comprising a second conductive particle adjacent to a side surface of the second conductive layer.

7. A memory element comprising:

a first conductive layer over an insulating surface;

an insulating film over the insulating surface and over a part of the first conductive layer to expose a portion of the first conductive layer;

a second conductive layer over the insulating film wherein the second conductive layer partly overlaps the first conductive layer with the insulating film interposed therebetween; and

a first conductive particle over the exposed portion of the first conductive layer,

wherein the first and second conductive layers are electrically connectable to each other at least through the first conductive particle as a result in a writing operation of the memory element.

8. A memory element according to claim 7,

wherein the first conductive particle is a conductive fine particle having a grain size of greater than or equal to 5 nm and lass than or equal to 30 nm.

9. A memory element according to claim 7,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

10. A memory element according to claim 7,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line.

14. A memory element according to claim 7, further comprising a second conductive particle over the second conductive layer.

15. A memory element according to claim 7, further comprising a second conductive particle adjacent to a side surface of the second conductive layer.