Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

• US 8,432,000 B2
• Filed: 06/18/2010
• Issued: 04/30/2013
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E.
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): KIM, SU C
• Application Number:
  US12/819,023
• Publication Number:
  US 20110309469A1
• Time in Patent Office: 1,047 Days
• Field of Search: 257/262, 257/272, 257/369, 257/368, 257/371, 257/374, 257/377, 257/383, 257/384, 257/396, 257/397, 257/647, 257/E29.02, 257/E29.271, 257/E21.552, 257/E21.553, 257/E21.555, 438/135, 438/142, 438/151, 438/199, 438/197, 438/201, 438/207, 438/216, 438/225, 438/226, 438/228, 438/230, 438/297, 438/362, 438/363, 438/439, 438/442
• US Class Current: 257/374
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Claims

1. A semiconductor device comprising:

an epitaxial layer;

a field oxide disposed in the epitaxial layer, the field oxide extending into the epitaxial layer;

a first trench having a sidewall and disposed in the epitaxial layer;

a second trench having a sidewall and disposed in the epitaxial layer;

a mesa disposed between the first trench and the second trench, the mesa having a top surface substantially coplanar with a top surface of the field oxide;

a shield dielectric having a first portion lining the sidewall of the first trench and having a second portion covering at least a portion of the top surface of the field oxide;

a polysilicon disposed in the first trench; and

a substantially planar surface including the top surface of the polysilicon, a bottom surface of the second portion of the shield dielectric, and the top surface of the mesa.

2. The semiconductor device of claim 1 wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).

3. The semiconductor device of claim 1, wherein the substantially planar surface is contiguous with the top surface of the polysilicon, the second portion of the shield dielectric, and the top surface of the mesa.

4. The semiconductor device of claim 1, further comprising:

a top metal; and

a dielectric layer and a solderable top metal layer disposed over the top metal,

the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.

5. The semiconductor device of claim 4, wherein the dielectric layer includes polyimide.

6. The semiconductor device of claim 1, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;

a top metal disposed above the silicide layer; and

a solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.

7. The semiconductor device of claim 1, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.

8. A semiconductor device comprising:

an epitaxial layer;

a field oxide disposed in the epitaxial layer;

a trench having a sidewall and disposed in the epitaxial layer;

a mesa disposed between the trench and the field oxide;

a dielectric having a first portion lining the sidewall of the trench and having a second portion covering at least a portion of a top surface of the field oxide;

a polysilicon disposed in the trench; and

a substantially planar surface including a top surface of the polysilicon, a top surface of the dielectric, a top surface of the mesa, and a top surface of the field oxide.

9. The semiconductor device of claim 8, further comprising:

a top metal having a portion disposed on the second portion of the dielectric; and

a dielectric layer and a solderable top metal layer disposed over at least a portion of the top metal, the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.

10. The semiconductor device of claim 8, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).

11. The semiconductor device of claim 8, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.

12. The semiconductor device of claim 8, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.

13. The semiconductor device of claim 8, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer and at least a portion of the polysilicon, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;

a top metal disposed above the silicide layer; and

a solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.

14. A semiconductor device comprising:

an epitaxial layer;

a field oxide disposed in the epitaxial layer;

a trench having a sidewall and disposed in the epitaxial layer;

a mesa disposed between the trench and the field oxide;

a first dielectric lining the sidewall of the trench;

a second dielectric disposed on at least a portion of the field oxide;

a polysilicon disposed in the trench; and

a substantially planar surface including a top surface of the polysilicon, a top surface of the first dielectric, a bottom surface of the second dielectric, and a top surface of the mesa.

15. The semiconductor device of claim 14, further comprising:

a top metal having a portion disposed on the second dielectric; and

a dielectric layer and a solderable top metal layer disposed over at least a portion of the top metal, the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.

16. The semiconductor device of claim 14, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).

17. The semiconductor device of claim 14, wherein the substantially planar surface is contiguous with the top surface of the polysilicon, the second dielectric, and the top surface of the mesa.

18. The semiconductor device of claim 14, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.

19. The semiconductor device of claim 14, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer, the silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.

20. The semiconductor device of claim 14, further comprising:

a silicide layer disposed on at least a portion of the epitaxial layer and at least a portion of the polysilicon, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;

a top metal disposed above the silicide layer; and

a solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.