Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
First Claim
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1. A semiconductor device comprising:
- an epitaxial layer;
a field oxide disposed in the epitaxial layer, the field oxide extending into the epitaxial layer;
a first trench having a sidewall and disposed in the epitaxial layer;
a second trench having a sidewall and disposed in the epitaxial layer;
a mesa disposed between the first trench and the second trench, the mesa having a top surface substantially coplanar with a top surface of the field oxide;
a shield dielectric having a first portion lining the sidewall of the first trench and having a second portion covering at least a portion of the top surface of the field oxide;
a polysilicon disposed in the first trench; and
a substantially planar surface including the top surface of the polysilicon, a bottom surface of the second portion of the shield dielectric, and the top surface of the mesa.
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Abstract
High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
375 Citations
20 Claims
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1. A semiconductor device comprising:
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an epitaxial layer; a field oxide disposed in the epitaxial layer, the field oxide extending into the epitaxial layer; a first trench having a sidewall and disposed in the epitaxial layer; a second trench having a sidewall and disposed in the epitaxial layer; a mesa disposed between the first trench and the second trench, the mesa having a top surface substantially coplanar with a top surface of the field oxide; a shield dielectric having a first portion lining the sidewall of the first trench and having a second portion covering at least a portion of the top surface of the field oxide; a polysilicon disposed in the first trench; and a substantially planar surface including the top surface of the polysilicon, a bottom surface of the second portion of the shield dielectric, and the top surface of the mesa. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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an epitaxial layer; a field oxide disposed in the epitaxial layer; a trench having a sidewall and disposed in the epitaxial layer; a mesa disposed between the trench and the field oxide; a dielectric having a first portion lining the sidewall of the trench and having a second portion covering at least a portion of a top surface of the field oxide; a polysilicon disposed in the trench; and a substantially planar surface including a top surface of the polysilicon, a top surface of the dielectric, a top surface of the mesa, and a top surface of the field oxide. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A semiconductor device comprising:
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an epitaxial layer; a field oxide disposed in the epitaxial layer; a trench having a sidewall and disposed in the epitaxial layer; a mesa disposed between the trench and the field oxide; a first dielectric lining the sidewall of the trench; a second dielectric disposed on at least a portion of the field oxide; a polysilicon disposed in the trench; and a substantially planar surface including a top surface of the polysilicon, a top surface of the first dielectric, a bottom surface of the second dielectric, and a top surface of the mesa. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification