Method and structure of monolithetically integrated inertial sensor using IC foundry-compatible processes

• US 8,432,005 B2
• Filed: 06/12/2012
• Issued: 04/30/2013
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao (Charles)
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US13/494,986
• Publication Number:
  US 20120248506A1
• Time in Patent Office: 322 Days
• Field of Search: 257/252, 257/254, 257/414, 257/415, 257/417, 257/418, 257/419, 257/420
• US Class Current: 257/414
• CPC Class Codes: B81B 2201/025 Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

The present invention relates to integrating an inertial mechanical device on top of a CMOS substrate monolithically using IC-foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A thick silicon layer is added on top of the CMOS. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level.

Comparing to the incumbent bulk or surface micromachined MEMS inertial sensors, the vertically monolithically integrated inertial sensors have smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.

Claims

1. A monolithic MEMS and CMOS integrated circuit device comprising:

a first semiconductor substrate having a first surface region;

one or more CMOS integrated circuit devices provided on a CMOS integrated circuit device region overlying the first surface region, the CMOS integrated circuit device region having a CMOS surface region;

a dielectric region overlying the CMOS surface region, the dielectric region having a cavity region provided therein;

a second semiconductor substrate having a second surface region overlying the dielectric region and enclosing the cavity region, the second semiconductor substrate having a spring region overlying a vicinity of the cavity region;

a first piezo resistor device provided within a first portion of the spring region of the second semiconductor substrate;

a second piezo resistor device provided within a second portion of the spring region of the second semiconductor substrate; and

a mass of material coupled to a portion of the spring region of the second semiconductor substrate between the second piezo resistor device and the first piezo resistor device, the mass material being overlying the cavity region and coupled to the spring region to be movable from at least a first position to a second position and to be sensed respectively by either or both the first piezo resistor device and the second piezo resistor device.

2. The device of claim 1 wherein the dielectric layer comprises one or more patterned regions.

3. The device of claim 1 wherein the second semiconductor comprises a desired thickness and a polished surface region.

4. The device of claim 3 wherein the second semiconductor comprises one or more via structures formed within one or more portions of the second semiconductor substrate.

5. The device of claim 4 wherein the one or more via structures extend from the second surface region to a vicinity of the desired thickness.

6. The device of claim 4 wherein the one or more via structures are configured as stop structures.

7. The device of claim 4 wherein the second semiconductor substrate comprises an SOI substrate having a bulk portion, overlying insulating layer, and single crystal device layer.

8. The device of claim 4 further comprising an enclosure layer overlying the first and second piezo resistor devices.

9. The device of claim 8 wherein the enclosure layer comprises a titanium material, the titanium material being activated as a getter layer.

10. The device of claim 8 wherein the enclosure layer is selected from a group consisting of:

a metal, a semiconductor material, an amorphous silicon material, a dielectric layer, or a combination of these layers.

11. The device of claim 8 wherein the enclosure layer comprises an open region between the first and second piezo resistor devices and the enclosure layer.

12. The device of claim 11 further comprising an encapsulating layer overlying the enclosure layer, the encapsulating layer substantially sealing the first and second piezo resistor devices to form a predetermined environment within the open region.

13. The device of claim 12 wherein the encapsulating layer is selected from a group consisting of:

a metal layer, a spin on glass, spray on glass, amorphous silicon, a dielectric layer, or any combination of these layers.

14. The device of claim 12 wherein the predetermined environment comprises an inert gas at a determined pressure.

15. A monolithic MEMS and CMOS integrated circuit device comprising:

a first semiconductor substrate having a first surface region;

one or more CMOS integrated circuit devices provided on a CMOS integrated circuit device region overlying the first surface region, the CMOS integrated circuit device region having a CMOS surface region;

a dielectric region overlying the CMOS surface region, the dielectric region having a cavity region provided therein;

a second semiconductor substrate having a second surface region overlying the dielectric region and enclosing the cavity region, the second semiconductor substrate having a spring region overlying a vicinity of the cavity region;

one or more free standing MEMS structures formed within one or more portions of the second semiconductor substrate;

a mass of material coupled to a portion of the spring region of the second semiconductor substrate, the mass material being overlying the cavity region and coupled to the spring region to be movable from at least a first position to a second position and to be sensed by the one or more free standing MEMS structures;

an enclosure layer overlying the one or more free standing MEMS structures, the enclosure layer comprising an open region between the free standing MEMS structures and the enclosure layer; and

an encapsulating layer overlying the enclosure layer, the encapsulating layer substantially sealing the one or more free standing MEMS structures to form a predetermined environment within the open region.

16. The device of claim 15 wherein the second semiconductor substrate comprises an SOI substrate having a bulk portion, overlying insulating layer, and single crystal device layer.

17. The device of claim 15 wherein the enclosure layer comprises a titanium material, the titanium material being activated as a getter layer.

18. The device of claim 15 wherein the enclosure layer is selected from a group consisting of:

a metal, a semiconductor material, an amorphous silicon material, a dielectric layer, or a combination of these layers.

19. The device of claim 15 wherein the encapsulating layer is selected from a group consisting of:

a metal layer, a spin on glass, spray on glass, amorphous silicon, a dielectric layer, or any combination of these layers.

20. A monolithic MEMS and CMOS integrated circuit device comprising:

a first semiconductor substrate having a first surface region;

one or more CMOS integrated circuit devices provided on a CMOS integrated circuit device region overlying the first surface region, the CMOS integrated circuit device region having a CMOS surface region;

a dielectric region overlying the CMOS surface region, the dielectric region having a cavity region provided therein;

a second semiconductor substrate having a second surface region overlying the dielectric region and enclosing the cavity region, the second semiconductor substrate having a spring region overlying a vicinity of the cavity region;

a first piezo resistor device provided within a first portion of the spring region of the second semiconductor substrate;

a second piezo resistor device provided within a second portion of the spring region of the second semiconductor substrate;

a mass of material coupled to a portion of the spring region of the second semiconductor substrate between the second piezo resistor device and the first piezo resistor device, the mass material being overlying the cavity region and coupled to the spring region to be movable from at least a first position to a second position and to be sensed respectively by either or both the first piezo resistor device and the second piezo resistor device;

an enclosure layer overlying the first and second piezo resistor devices, the enclosure layer comprising an open region between the first and second piezo resistor devices and the enclosure layer; and

an encapsulating layer overlying the enclosure layer, the encapsulating layer substantially sealing the first and second piezo resistor devices to form a predetermined environment within the open region.