Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same

• US 8,432,012 B2
• Filed: 03/18/2011
• Issued: 04/30/2013
• Est. Priority Date: 08/01/2006
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Henning, Jason
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US13/051,606
• Publication Number:
  US 20110248285A1
• Time in Patent Office: 774 Days
• Field of Search: 257/106, 257/112, 257/155, 257/260, 257/471, 257/472, 257/474, 257/484, 257/928, 257/E27.04, 257/E29.338, 257/E31.065, 257/E31.066
• US Class Current: 257/471
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0495 Schottky electrodes
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined, and a plurality of spaced apart doped regions within the active region. The plurality of doped regions have a second conductivity type that is opposite the first conductivity type and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of doped regions include a plurality of rows extending in a longitudinal direction. Each of the rows includes a plurality of longitudinally extending segments, and the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction.

Claims

1. A semiconductor device, comprising:

a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;

a plurality of spaced apart doped regions within the active region, the plurality of doped regions having a second conductivity type that is opposite the first conductivity type and defining a plurality of exposed portions of the semiconductor layer within the active region;

wherein the plurality of doped regions comprise a plurality of rows extending in a longitudinal direction, each of the rows including a plurality of longitudinally extending segments; and

wherein the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction.

2. The semiconductor device of claim 1, wherein a first longitudinally extending segment in the first row at least partially overlaps two longitudinally extending segments in the adjacent row in the lateral direction.

3. The semiconductor device of claim 1, wherein longitudinally adjacent ones of the longitudinally extending segments in the first row are spaced apart by a distance L, and laterally adjacent ones of the longitudinally extending segments in adjacent rows are spaced apart by a distance W, wherein L is about equal to W.

4. The semiconductor device of claim 1, wherein any point in the active region of the semiconductor device is at least as close to at least one of the longitudinally extending segments as one half of a spacing between overlapping portions of laterally adjacent ones of the longitudinally extending segments in adjacent rows.

5. The semiconductor device of claim 1, wherein any point in the active region of the semiconductor device is at least as close to at least one of the longitudinally extending segments as one half of a spacing between longitudinally adjacent ones of the longitudinally extending segments in a row.

6. The semiconductor device of claim 1, further comprising a metal region in contact with the exposed portions of the semiconductor layer and the doped regions.

7. The semiconductor device of claim 6, wherein the semiconductor layer comprises a silicon carbide semiconductor layer.

8. The semiconductor device of claim 7, wherein the doped regions comprise p-type silicon carbide having a dopant concentration of from about 1×

10¹⁷ to about 1×

10¹⁸ cm<sup>−

3</sup>.

9. The semiconductor device of claim 1, further comprising a second doped region in the semiconductor layer, the second doped region having a doping concentration that is greater than a doping concentration of the doped regions, wherein the plurality of doped regions and the second doped region are located at the surface of the semiconductor layer, and wherein a ratio of a surface area occupied by the plurality of doped regions and the second doped region to a total surface area of the active region of the diode is less than about 0.4.

10. The semiconductor device of claim 9, further comprising a metal layer on the semiconductor layer and forming a Schottky junction with the exposed portions of the semiconductor layer, wherein a turn-on voltage of a p-n junction between the second doped region and the semiconductor layer is higher than a turn-on voltage of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer.

11. The semiconductor device of claim 10, wherein the doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the doped regions and the semiconductor layer occurs at a lower voltage than breakdown of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer.

12. The semiconductor device of claim 1, further comprising an edge termination region, wherein the doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the doped regions and the semiconductor layer occurs at a lower voltage than a breakdown voltage of the edge termination region.