Increased I/O leadframe and semiconductor device including same

• US 8,432,023 B1
• Filed: 06/15/2011
• Issued: 04/30/2013
• Est. Priority Date: 10/06/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Gi Jeong, Choi, Yeon Ho, Kim, Wan Jong
• Primary Examiner(s): Tran, Long
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US13/161,380
• Time in Patent Office: 685 Days
• Field of Search: 257/675, 257/670, 257/692, 257/E23.011
• US Class Current: 257/670
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor package, comprising:

a generally planar die pad residing on a first plane;

a plurality of land leads at least partially circumventing the die pad, each of the land leads residing on the first plane;

a plurality of support bars connected to and extending generally perpendicularly from multiple peripheral edge segments of the die pad, each of the support bars extending at least partially between a respective adjacent pair of the land leads;

a plurality of peripheral leads at least partially circumventing the land leads, each of the peripheral leads at least partially residing on a second plane which extends in spaced, generally parallel relation to the first plane;

a semiconductor die attached to the die pad and electrically connected to at least some of the land and peripheral leads; and

a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the die pad, the land and peripheral leads, and the semiconductor die such that portions of the land leads are exposed in the bottom surface of the package body, and portions of the peripheral leads protrude from the side surface thereof.

2. The semiconductor package of claim 1 wherein each of the support bars is half etched and encapsulated by the package body.

3. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to least some of the land and peripheral leads by conductive wires which are encapsulated by the package body.

4. The semiconductor package of claim 1 wherein the die pad has a generally quadrangular configuration defining the multiple peripheral edge segments, and the land and peripheral leads are segregated into at least four sets which each extend along respective ones of the peripheral edge segments of the die pad.

5. The semiconductor package of claim 4 wherein at least one of the support bars extends from each of the peripheral edge segments of the die pad and between an adjacent pair of the land leads of a corresponding set thereof.

6. The semiconductor package of claim 5 wherein each of the support bars is half etched and encapsulated by the package body.

7. The semiconductor package of claim 1 wherein a portion of the die pad is exposed in the bottom surface of the package body.

8. The semiconductor package of claim 1 wherein each of the land leads includes at least one locking protrusion which extends therefrom and is encapsulated by the package body.

9. The semiconductor package of claim 1 further comprising a plurality of extension leads at least partially circumventing the land leads, each of the extension leads being formed to include segments which reside on at least each of the first and second planes and being at least partially encapsulated by the package body such that portions of the extension leads are exposed in the bottom surface thereof.

10. The semiconductor package of claim 9 wherein each of the extension leads extends at least partially between a respective adjacent pair of the peripheral leads.

11. The semiconductor package of claim 9 wherein each of the land leads is linearly aligned with a respective one of the extension leads.

12. A semiconductor package, comprising:

a generally quadrangular die pad defining multiple peripheral edge segments;

a plurality of land leads segregated into at least four sets which each extend along respective ones of the peripheral edge segments of the die pad;

a plurality a support bars connected to and extending from the die pad, at least one of the support bars extending generally perpendicularly from each of the peripheral edge segments of the die pad and between an adjacent pair of the land leads of a corresponding set thereof;

a plurality of peripheral leads segregated into at least four sets which each extend along respective ones of the four sets of the land leads;

a semiconductor die attached to the die pad and electrically connected to at least some of the land and peripheral leads; and

a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the die pad, the land and peripheral leads, and the semiconductor die such that portions of the land leads are exposed in the bottom surface of the package body, and portions of the peripheral leads protrude from the side surface thereof.

13. The semiconductor package of claim 12 wherein each of the support bars is half etched and encapsulated by the package body.

14. The semiconductor package of claim 12 wherein the semiconductor die is electrically connected to least some of the land and peripheral leads by conductive wires which are encapsulated by the package body.

15. The semiconductor package of claim 12 wherein a portion of the die pad is exposed in the bottom surface of the package body.

16. The semiconductor package of claim 12 wherein each of the land leads includes at least one locking protrusion which extends therefrom and is encapsulated by the package body.

17. The semiconductor package of claim 12 further comprising a plurality of extension leads segregated into at least four sets which each extend along respective ones of the four sets of the land leads, the extension leads being at least partially encapsulated by the package body such that portions of the extension leads are exposed in the bottom surface thereof.

18. The semiconductor package of claim 17 wherein each of the extension leads extends at least partially between a respective adjacent pair of the peripheral leads.

19. The semiconductor package of claim 17 wherein each of the land leads is linearly aligned with a respective one of the extension leads.

20. A semiconductor package, comprising:

a generally planar die pad;

a plurality of land leads at least partially circumventing the die pad;

a plurality a support bars connected to and extending from the die pad, each of the support bars extending at least partially between a respective adjacent pair of the land leads;

a plurality of peripheral leads at least partially circumventing the land leads;

a semiconductor die attached to the die pad and electrically connected to at least some of the land and peripheral leads; and

a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the die pad, the land and peripheral leads, and the semiconductor die such that portions of the land leads are exposed in the bottom surface of the package body, and portions of the peripheral leads protrude from the side surface thereof, wherein each of the plurality of support bars include half-etched portions that define bottom surfaces encapsulated by the package body.