Through-silicon via structure and a process for forming the same

• US 8,432,038 B2
• Filed: 05/20/2010
• Issued: 04/30/2013
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Weng-Jin, Lin, Yung-Chi, Chiou, Wen-Chih
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US12/783,973
• Publication Number:
  US 20100314758A1
• Time in Patent Office: 1,076 Days
• Field of Search: 438/629, 438/637, 438/639, 438/642, 438/643, 438/649, 438/651, 257/773, 257/E21.577, 257/E21.585
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Claims

1. A device, comprising:

a semiconductor substrate having a front surface and a back surface and including an integrated circuit (IC) component formed on the front surface;

an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;

a contact plug formed in the ILD layer and electrically coupled to the IC component; and

a via structure formed in the ILD layer and extending through the semiconductor substrate, wherein the via structure comprises a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer sandwiched between at least a portion of the metal layer and at least a portion of the metal seed layer.

2. The device of claim 1, wherein the metal silicide layer comprises copper.

3. The device of claim 1, wherein the metal layer comprises copper, and the metal seed layer comprises copper.

4. The device of claim 1, wherein the barrier layer comprises TaN, Ta, TiN, Ti or combinations thereof.

5. The device of claim 1, wherein the via structure comprises a passivation layer surrounding the barrier layer.

6. The device of claim 5, wherein the passivation layer comprises silicon oxide.

7. The device of claim 1, wherein the via structure includes an end exposed on the back surface of the semiconductor substrate.

8. The device of claim 1, further comprising a semiconductor component stacked on the back surface of the semiconductor substrate and electrically connected to the via structure.

9. A semiconductor device, comprising:

a semiconductor substrate having a front surface and a back surface and including an integrated circuit (IC) component formed on the front surface;

an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;

a contact plug formed in the ILD layer and electrically coupled to the IC component; and

a via structure formed in the ILD layer and extending through the semiconductor substrate;

wherein the via structure comprises a copper layer, a copper seed layer surrounding the copper layer, a barrier layer surrounding the copper seed layer, and a copper silicide layer sandwiched between at least a portion of the copper layer and at least a portion of the copper seed layer; and

wherein the via structure includes an end exposed on the back surface of the semiconductor substrate.

10. The semiconductor device of claim 9, wherein the barrier layer comprises TaN, Ta, TiN, Ti or combinations thereof.

11. The semiconductor device of claim 9, further comprising a passivation layer surrounding the barrier layer.

12. The semiconductor device of claim 11, wherein the passivation layer comprises silicon oxide.

13. The semiconductor device of claim 9, further comprising

a backside dielectric layer formed overlying the back surface of the semiconductor substrate;

and

an external contact formed on the backside dielectric layer.

14. The semiconductor device of claim 13, wherein the external contact comprises solder bumps, copper-containing bumps or combinations thereof.