Array column integrator

• US 8,432,149 B2
• Filed: 06/30/2011
• Issued: 04/30/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Levine, Peter
• Primary Examiner(s): Vazquez, Arleen M
• Application Number:
  US13/174,465
• Publication Number:
  US 20120001615A1
• Time in Patent Office: 670 Days
• Field of Search: 324/71.5, 324/713, 257/253, 327/336, 327/337, 327/345
• US Class Current: 324/71.5
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

The described embodiments may provide a chemical detection circuit with an improved signal-to-noise ration. The chemical detection circuit may include a current source, a chemical detection pixel, an amplifier and a capacitor. The chemical detection pixel may comprise a chemical-sensitive transistor that may have a first and second terminals and a row-select switch coupled between the current source and chemically-sensitive transistor. The amplifier may have a first input and a second input, with the first input coupled to an output of the chemically-sensitive transistor via a switch and the second input coupled to an offset voltage line. The capacitor may be coupled between an output of the amplifier and the first input of the amplifier. The capacitor and amplifier may form an integrator and may be shared by a column of chemical detection pixels.

Claims

1. A device comprising:

a chemically-sensitive field-effect transistor (chemFET) including a first terminal and a second terminal, and a floating gate coupled to a passivation layer; and

an integrator circuit coupled to the second terminal of the chemFET via a data line, the integrator circuit to;

bias the first terminal of the chemFET to a first bias voltage during a read interval;

induce current through the chemFET via the data line during the read interval; and

generate an output signal proportional to an integral of a voltage or current on the data line in response to the induced current through the chemFET during the read interval.

2. The device of claim 1, wherein the output signal indicates an ion-concentration of an analyte solution exposed to the passivation layer during the read interval.

3. The device of claim 1, wherein the integrator circuit comprises:

an operational amplifier having a first input coupled to a voltage source, a second input coupled to the data line, and an output to generate the output signal; and

a capacitor coupled between the second input of the operational amplifier and the output.

4. The device of claim 3, further comprising a reference current source to provide a reference current to the data line during the read interval, and wherein the capacitor integrates a difference in current between the reference current and the induced current through the chemFET during the read interval.

5. The device of claim 3, further comprising:

a current source to produce a bias current through the chemFET during the read interval, thereby establishing a voltage on the second terminal of the chemFET based on a threshold voltage of the chemFET; and

a resistive element coupled between the second terminal of the chemFET and a sensing node coupled to the second input of the operational amplifier to bias the sensing node to a second bias voltage, and wherein the capacitor integrates a difference in voltage between the second terminal of the chemFET and the second bias voltage during the read interval.

6. The device of claim 5, wherein the resistive element is a resistor.

7. The device of claim 5, wherein the resistive element is a pass transistor having a first terminal coupled to the second terminal of the chemFET, and a second terminal coupled to the sensing node.