Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

• US 8,432,187 B2
• Filed: 12/07/2010
• Issued: 04/30/2013
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US12/962,041
• Publication Number:
  US 20110187410A1
• Time in Patent Office: 875 Days
• Field of Search: None
• US Class Current: 326/46
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Claims

1. A latch circuit comprising:

a latch portion; and

a data holding portion operationally connected to the latch portion to hold data of the latch portion,

the latch portion comprising;

a transistor,

wherein a channel formation region of the transistor of the latch portion includes crystalline silicon,

the data holding portion comprising;

a transistor; and

a capacitor having a pair of electrodes,

wherein a channel formation region of the transistor of the data holding portion includes an oxide semiconductor layer, and

wherein one of a source and a drain of the transistor of the data holding portion is electrically connected to one of the electrodes of the capacitor.

2. The latch circuit according to claim 1, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

3. The latch circuit according to claim 1, wherein the transistor of the data holding portion controls writing of data into the capacitor.

4. The latch circuit according to claim 1, wherein the transistor of the data holding portion has a function of holding data in the capacitor.

5. The latch circuit according to claim 1, wherein the transistor of the data holding portion has a function of reading data held in the capacitor to the latch portion.

6. A logic circuit, wherein a plurality of latch circuits according to claim 1 is included.

7. A semiconductor device including a logic circuit, the logic circuit including the latch circuit according to claim 1.

8. The latch circuit according to claim 1, wherein the oxide semiconductor layer includes crystal.

9. A latch circuit comprising:

a latch portion; and

a data holding portion operationally connected to the latch portion to hold data of the latch portion,

the latch portion comprising;

a first element; and

a second element,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and

wherein each of the first element and the second element comprises a transistor, the transistor comprising a channel formation region which includes crystalline silicon, and

the data holding portion comprising;

a transistor; and

a capacitor having a pair of electrodes,

wherein a channel formation region of the transistor of the data holding portion includes an oxide semiconductor layer,

wherein one of a source and a drain of the transistor of the data holding portion is electrically connected to one of the electrodes of the capacitor, and

wherein the other of the source and the drain of the transistor of the data holding portion is electrically connected to the input of the first element.

10. The latch circuit according to claim 9, wherein the first element is an inverter and the second element is an inverter.

11. The latch circuit according to claim 9, wherein the latch portion comprises:

a first switch; and

a second switch,

wherein the output of the second element is electrically connected to the input of the first element through the second switch, and

wherein the input of the first element is electrically connected to a wiring supplied with an input signal through the first switch.

12. The latch circuit according to claim 9, wherein the first element is a NAND and the second element is a clocked inverter.

13. The latch circuit according to claim 9, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

14. A logic circuit, wherein a plurality of latch circuits according to claim 9 is included.

15. A semiconductor device including a logic circuit, the logic circuit including the latch circuit according to claim 9.

16. The latch circuit according to claim 9, wherein the oxide semiconductor layer includes crystal.

17. A latch circuit comprising:

a latch portion;

the latch portion comprising;

a transistor,

wherein a channel formation region of the transistor of the latch portion includes crystalline silicon,

a data holding portion operationally connected to the latch portion to hold data of the latch portion,

the data holding portion comprising;

a first transistor;

a second transistor;

a first capacitor having a pair of electrodes; and

a second capacitor having a pair of electrodes,

wherein channel formation regions of the first transistor and the second transistor each include an oxide semiconductor layer,

wherein one of a source and a drain of the first transistor is electrically connected to one of the electrodes of the first capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the latch portion,

wherein one of a source and a drain of the second transistor is electrically connected to one of the electrodes of the second capacitor, and

wherein the other of the source and the drain of the second transistor is electrically connected to an output of the latch portion.

18. The latch circuit according to claim 17, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

19. The latch circuit according to claim 17, wherein the first transistor controls writing of data into the first capacitor, and wherein the second transistor controls writing of data into the second capacitor.

20. The latch circuit according to claim 17, wherein the first transistor has a function of holding data in the first capacitor, and wherein the second transistor has a function of holding data in the second capacitor.

21. The latch circuit according to claim 17, wherein the first transistor has a function of reading data held in the first capacitor to the latch portion, and wherein the second transistor has a function of reading data held in the second capacitor to the latch portion.

22. A logic circuit, wherein a plurality of latch circuits according to claim 17 is included.

23. A semiconductor device including a logic circuit, the logic circuit including the latch circuit according to claim 17.

24. The latch circuit according to claim 17, wherein the oxide semiconductor layer includes crystal.

25. A latch circuit comprising:

a latch portion; and

a data holding portion configured to hold data of the latch portion,

the latch portion comprising;

a first element; and

a second element,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element,

wherein each of the first element and the second element comprises a transistor, the transistor comprising a channel formation region which includes crystalline silicon, and

the data holding portion comprising;

a first transistor;

a second transistor;

a first capacitor having a pair of electrodes; and

a second capacitor having a pair of electrodes,

wherein channel formation regions of the first transistor and the second transistor each include an oxide semiconductor layer,

wherein one of a source and a drain of the first transistor is electrically connected to one of the electrodes of the first capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to the input of the first element,

wherein one of a source and a drain of the second transistor is electrically connected to one of the electrodes of the second capacitor, and

wherein the other of the source and the drain of the second transistor is electrically connected to the output of the first element.

26. A latch circuit according to claim 25, wherein the latch portion comprises:

a first switch; and

a second switch,

wherein the output of the second element is electrically connected to the input of the first element through the second switch, and

wherein the input of the first element is electrically connected to a wiring supplied with the input signal through the first switch.

27. A latch circuit according to claim 25, wherein the first element is a NAND and the second element is a clocked inverter.

28. The latch circuit according to claim 25, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

29. A logic circuit, wherein a plurality of latch circuits according to claim 25 is included.

30. A semiconductor device including a logic circuit, the logic circuit including the latch circuit according to claim 25 is used.

31. The latch circuit according to claim 25, wherein the oxide semiconductor layer includes crystal.

32. A CPU comprising:

a logic circuit,

the logic circuit comprising;

a latch circuit,

the latch circuit comprising;

a latch portion; and

a data holding portion operationally connected to the latch portion to hold data of the latch portion,

the latch portion comprising;

a transistor,

wherein a channel formation region of the transistor of the latch portion includes crystalline silicon,

the data holding portion comprising;

a transistor; and

a capacitor having a pair of electrodes,

wherein a channel formation region of the transistor of the data holding portion includes an oxide semiconductor layer,

wherein one of a source and a drain of the transistor of the data holding portion is electrically connected to one of the electrodes of the capacitor.

33. The CPU according to claim 32, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

34. The CPU according to claim 32, wherein the oxide semiconductor layer includes crystal.

35. A CPU comprising:

a logic circuit,

the logic circuit comprising;

a latch circuit,

the latch circuit comprising;

a latch portion; and

a data holding portion operationally connected to the latch portion to hold data of the latch portion,

the latch portion comprising;

a transistor,

wherein a channel formation region of the transistor of the latch portion includes crystalline silicon,

the data holding portion comprising;

a first transistor;

a second transistor;

a first capacitor having a pair of electrodes; and

a second capacitor having a pair of electrodes,

wherein channel formation regions of the first transistor and the second transistor each include an oxide semiconductor layer,

wherein one of a source and a drain of the first transistor is electrically connected to one of the electrodes of the first capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the latch portion,

wherein one of a source and a drain of the second transistor is electrically connected to one of the electrodes of the second capacitor, and

wherein the other of the source and the drain of the second transistor is electrically connected to an output of the latch portion.

36. The CPU according to claim 35, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

37. The CPU according to claim 35, wherein the oxide semiconductor layer includes crystal.