Digital voltage level shifter

• US 8,432,189 B1
• Filed: 01/23/2012
• Issued: 04/30/2013
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Goyal, Gaurav, Lohani, Umesh Chandra, Malhan, Bipin B.
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/356,615
• Time in Patent Office: 463 Days
• Field of Search: 326/62, 326/68, 326 80- 81, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A dual supply bidirectional level shifter performs voltage level shifting in two directions, low to high and high to low. A feedback control branch and a control stage inverter are provided that reduce leakage power and allow for low delay time while also allowing for a small circuit footprint.

Claims

1. A level shifter that converts an input signal at a first voltage level to an output signal at a second voltage level different from the first voltage level, the level shifter comprising:

a voltage translation stage connected between a higher voltage source and ground, and including a first inverter that receives the input signal at the first voltage level and generates an intermediate signal at the second voltage level;

a driver stage connected between the higher voltage source and ground, and including a second inverter connected to the first inverter and receiving the intermediate signal and generating the output signal at the second voltage level; and

a control stage connected to the voltage translation stage and the driver stage, the control stage including,

a feedback circuit branch connected between the higher voltage source and ground, and

a control stage inverter connected between a lower voltage source and ground, wherein the control stage inverter receives the input signal and generates a control stage inverter output that is provided as an input to the second inverter and to the feedback circuit branch, and wherein the feedback circuit branch also receives the intermediate signal and the output signal and generates a feedback branch output signal that is input to the voltage translation stage.

2. The level shifter of claim 1, wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series between the higher voltage supply and ground, wherein the first PMOS and first NMOS transistors receive the input signal at their gates and the intermediate signal is provided at a node between the drains of the first PMOS and NMOS transistors, which are connected together.

3. The level shifter of claim 2, wherein the voltage translation stage includes an additional transistor connected between the higher voltage source and the source of the first PMOS transistor and having a gate that receives the feedback branch output signal.

4. The level shifter of claim 3, wherein the second inverter of the driver stage comprises:

a second PMOS transistor having a source connected to the higher power supply, and a gate connected to the node between the drains of the first PMOS and NMOS transistors and receiving the intermediate signal; and

a second NMOS transistor having a drain connected to the drain of the second PMOS transistor, a source connected to ground, and a gate connected to the output of the control stage inverter, wherein the output signal is provided at a node between the drains of the second PMOS and NMOS transistors.

5. The level shifter of claim 4, wherein the feedback circuit branch comprises:

a first switch having a source connected to the higher power supply, and a gate that receives the intermediate signal generated by the first inverter;

a second switch having a drain connected to a drain of the first switch, and a gate that receives the output signal from the second inverter; and

a third switch having a drain connected to a source of the second switch, a source connected to ground, and a gate connected to the output of the control stage inverter and receiving the control stage inverter output.

6. The level shifter of claim 5, wherein the first switch is a PMOS device, and the second and third switches are NMOS devices.

7. The level shifter of claim 5, the control stage inverter comprises:

a PMOS transistor having a source connected to the lower voltage supply, and a gate that receives the input signal; and

a NMOS transistor having a drain connected to a drain of the control stage inverter PMOS transistor drain, a source connected to ground, and a gate connected to the gate of the gate of the control stage inverter PMOS transistor and receiving the input signal.

8. The level shifter of claim 7, wherein the control stage switch comprises a low-voltage threshold device.