Delay lock loop system with a self-tracking function and method thereof

• US 8,432,206 B2
• Filed: 03/20/2012
• Issued: 04/30/2013
• Est. Priority Date: 04/07/2011
• Status: Active Grant

• Current Assignee: Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Teng, Kuang-Fu, Shiah, Chun, Chang, Feng-Chia, Yuan, Der-Min
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/425,379
• Publication Number:
  US 20120256666A1
• Time in Patent Office: 406 Days
• Field of Search: 327/149, 327/158
• US Class Current: 327/158
• CPC Class Codes: H03L 1/02 against variations of temperature only
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

Claims

1. A delay lock loop system with a self-tracking function, the delay lock loop system comprising:

a timing controller for outputting an external enable signal periodically while a power saving signal is a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal;

a pulse generator for generating a pulse according to a positive edge of the power saving signal;

an OR gate having a first terminal for receiving the power saving signal, a second terminal coupled to the timing controller for receiving the external enable signal, a third terminal coupled to the pulse generator for receiving the pulse, and an output terminal for outputting an enable signal;

an input buffer for receiving an external clock, and outputting an adjusted clock; and

a delay lock loop (DLL) coupled to the OR gate and the input buffer for receiving the adjusted clock and the enable signal, the delay lock loop comprising a voltage control delay circuit for synchronizing a phase of the adjusted clock with a phase of an output clock of the delay lock loop, and the delay lock loop being enabled again according to the enable signal.

2. The delay lock loop system of claim 1, wherein the input buffer further is coupled to the OR gate for receiving the enable signal.

3. The delay lock loop system of claim 1, wherein the timing controller is used for receiving the external enable signal, and outputting the external enable signal according to a predetermined clock.

4. A method of self tracking of a delay lock loop system, the method comprising:

a timing controller outputting an external enable signal periodically;

disabling the timing controller according to a logic-high voltage of a power saving signal, and a pulse generator generating a pulse according to a positive edge of the power saving signal;

generating an enable signal according to the power saving signal, the external enable signal, and the pulse; and

enabling the delay lock loop again according to the enable signal.

5. The method of claim 4, further comprising:

enabling the delay lock loop and an input buffer again according to the enable signal.

6. A method of self tracking of a delay lock loop system, the method comprising:

a timing controller receiving an external enable signal;

the timing controller outputting the external enable signal according to a predetermined clock;

disabling the timing controller according to a logic-high voltage of a power saving signal, and a pulse generator generating a pulse according to a positive edge of the power saving signal;

generating an enable signal according to the power saving signal, the external enable signal, and the pulse; and

enabling the delay lock loop again according to the enable signal.

7. The method of claim 6, further comprising:

enabling the delay lock loop and an input buffer again according to the enable signal.