Panel and driving controlling method

• US 8,432,389 B2
• Filed: 03/11/2009
• Issued: 04/30/2013
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamamoto, Tetsuro, Uchino, Katsuhide
• Primary Examiner(s): SIMPSON, LIXI CHOW
• Application Number:
  US12/382,238
• Publication Number:
  US 20090244050A1
• Time in Patent Office: 1,511 Days
• Field of Search: None
• US Class Current: 345/212
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/0256 with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

The present invention provides a panel, including: a plurality of pixel circuits disposed in rows and columns and each including a light emitting element for emitting light in response to driving current, a sampling transistor for sampling an image signal, a driving transistor for supplying the driving current to the light emitting element, and a storage capacitor for storing a predetermined potential; and a power supplying section configured to supply a power supply voltage of a high potential or a low potential at a time to all of the pixel circuits arranged in rows and columns; the power supplying section setting the power supply voltage to be supplied to the low potential, with which the gate-source voltage of the driving transistor becomes higher than a threshold voltage of the driving transistor, by Q times within a one-field period, Q being equal to or greater than 2.

Claims

1. A panel, comprising:

a plurality of pixel circuits disposed in rows and columns and each including a light emitting element for emitting light in response to driving current, a sampling transistor for sampling an image signal, a driving transistor for supplying the driving current to the light emitting element, and a storage capacitor for storing a predetermined potential; and

power supplying means for supplying a power supply voltage to all of the pixel circuits and configured to selectively switch the power supply voltage between a high potential and a low potential for all of the pixel circuits simultaneously;

wherein the power supplying means is configured to switch the power supply voltage from the high potential to the low potential Q times within a one-field period, Q being equal to or greater than 2.

2. The panel according to claim 1, wherein, after one of the Q times within the one-field period that the power supply voltage is switched from the high potential to the low potential and before a next one of the Q times within the one-field period that the power supply voltage is switched from the high potential to the low potential, those of the pixel circuits which are included in two rows simultaneously carry out a threshold value correction preparation operation for making the gate-source voltage of the driving transistor higher than the threshold voltage of the driving transistor and thereafter simultaneously carry out a threshold value correction operation of storing a voltage corresponding to the threshold voltage of the driving transistor into the storage capacitor.

3. The panel according to claim 2, wherein the threshold value correction preparation operation for each of the pixel circuits ends when the power supply voltage is switched from the low potential to the high potential.

4. The panel according to claim 1, wherein, after one of the Q times within the one-field period that the power supply voltage is switched from the high potential to the low potential and before a next one of the Q times within the one-field period that the power supply voltage is switched from the high potential to the low potential, those of the pixel circuits which are included in two rows simultaneously carry out a threshold value correction preparation operation for making the gate-source voltage of the driving transistor higher than the threshold voltage of the driving transistor, and after the threshold value correction preparation operation ends, the pixel circuits in the two rows line-sequentially carry out a threshold value correction operation of storing a voltage corresponding to the threshold voltage of the driving transistor into the storage capacitor.

5. The panel according to claim 4, wherein, the threshold value correction preparation operation for each of the pixel circuits ends when the power supply voltage is switched from the low potential to the high potential.

6. The panel according to claim 1, further comprising image signal supplying means for supplying a signal potential which corresponds to a gradation represented by the image signal to the pixel circuits;

the image signal supplying means being configured to supply, while the power supply voltage is set to the low potential, a threshold value correction reference potential which is higher than the threshold voltage of the driving transistor and to selectively supply, while the power supply voltage is set to the high potential, a no-light emission potential for causing the light emitting element to emit no light and the signal potential.

7. The panel according to claim 6, wherein the no-light emission potential is lower than the sum of the cathode potential of the light emitting element, a threshold voltage of the light emitting element and the threshold voltage of the driving transistor.

8. The panel according to claim 6, wherein the no-light emission potential is equal to the threshold value correction reference potential.

9. The panel according to claim 1, wherein the one-field period comprises Q sub-periods, with each sub-period comprising a time period between successive times the power supply voltage is switched from the high potential to the low potential,

wherein the rows of pixel circuits are grouped into Q groups, each group comprising at least two of the rows of pixel circuits and each group corresponding, respectively, to one of the sub-periods,

wherein, for each respective group, those pixel circuits included in the rows of the respective group, during the sub-period to which the respective group corresponds, simultaneously carry out a threshold value correction preparation operation for making the gate-source voltage of the driving transistor higher than the threshold voltage of the driving transistor.

10. The panel according to claim 9, wherein, for each respective group, those pixel circuits included in the rows of the respective group, during the sub-period to which the respective group corresponds and after carrying out the threshold value correction preparation operation, carry out a threshold value correction operation of storing a voltage corresponding to the threshold voltage of the driving transistor into the storage capacitor.

11. The panel according to claim 10, wherein, for each respective group, those pixel circuits included in the rows of the respective group carry out the threshold value correction operation simultaneously.

12. The panel accordingly to claim 11, wherein, for each respective group the threshold value correction preparation operation ends and the threshold value correction operation begins when the power supply voltage is switched from the low potential to the high potential.

13. The panel according to claim 10, wherein, for each respective group:

the threshold value correction operation is carried out in a divided manner across a plurality of correction periods,

each row of the respective group carries out the threshold value correction operation in a first one of the correction periods simultaneously, the threshold value correction preparation operation ending and the first one of the correction periods beginning when the power supply voltage is switched from the low potential to the high potential, and

the threshold value correction operation is carried out line-sequentially in those of the correction periods other than the first one of the correction periods.

14. The panel according to claim 10, wherein, for each respective group, those pixel circuits included in the rows of the respective group carry out the threshold value correction operation line-sequentially.

15. The panel according to claim 14, further comprising image signal supplying means for supplying a signal potential which corresponds to a gradation represented by the image signal to the pixel circuits;

wherein the image signal supplying means is configured to supply, for each respective group;

while the threshold value correction preparation operation is being carried out, a first reference potential which is higher than the threshold voltage of the driving transistor,

while the threshold value correction operation is being carried out, a second reference potential for causing the light emitting element to emit no light, and

a third reference potential lower than the first reference potential to end the threshold value correction preparation operation.

16. The panel according to claim 9, further comprising image signal supplying means for supplying a signal potential that corresponds to a gradation represented by the image signal to the pixel circuits;

wherein the image signal supplying means is configured to supply, for each respective group, during the first one of the correction periods a first reference potential which is higher than the threshold voltage of the driving transistor and to supply during those of the correction periods other than the first one of the correction periods a second reference potential for causing the light emitting element to emit no light.

17. The panel according to claim 16, wherein the image signal supplying means is configured to supply, for each respective group, a third reference potential lower than the first reference potential to end the first of the correction periods.

18. The panel according to claim 9, wherein each of the groups comprises N≧

2 rows.

19. A driving controlling method for a panel which includes a plurality of pixel circuits disposed in rows and columns and each including a light emitting element for emitting light in response to driving current, a sampling transistor for sampling an image signal, a driving transistor for supplying the driving current to the light emitting element, and a storage capacitor for storing a predetermined potential, and power supplying means for supplying a power supply voltage to all of the pixel circuits and configured to selectively switch the power supply voltage between a high potential and a low potential for all of the pixel circuits simultaneously, the driving controlling method comprising:

switching the power supply voltage from the high potential to the low potential Q times within a one-field period, Q being equal to or greater than 2.