Semiconductor memory device

• US 8,432,718 B2
• Filed: 12/03/2010
• Issued: 04/30/2013
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): DINH, SON T
• Application Number:
  US12/960,117
• Publication Number:
  US 20110134680A1
• Time in Patent Office: 879 Days
• Field of Search: 365/104, 365/185.05, 365/177, 365/174
• US Class Current: 365/104
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

To provide a semiconductor memory device including an oxide semiconductor that can deal with instability of a threshold characteristic, in which writing is possible by a simple method. The semiconductor memory device functions by utilizing a characteristic that a threshold shifts when a thin film transistor including an oxide semiconductor is irradiated with ultraviolet light. Readout can be performed by setting a readout voltage between the threshold before the ultraviolet light irradiation and the threshold after irradiation. The threshold characteristic of an initial characteristic can be controlled by providing a back gate or by using two thin film transistors.

Claims

1. A semiconductor memory device comprising:

a bit comprising a thin film transistor;

a row decoder connected to a word line;

a column decoder configured to select a bit line; and

a readout circuit electrically connected to the bit line selected by the column decoder;

the thin film transistor comprising;

a first gate electrode;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer over the first insulating layer;

a source electrode and a drain electrode in electrical contact with the oxide semiconductor layer;

a second insulating layer over the source electrode and the drain electrode; and

a second gate electrode over the second insulating layer,

wherein the word line is connected to one of the first gate electrode and the second gate electrode,

wherein the bit line is connected to one of the source electrode and the drain electrode, and

wherein a portion of the other of the first gate electrode and the second gate electrode is capable of transmitting an ultraviolet light.

2. The semiconductor memory device according to claim 1, wherein the one of the first gate electrode and the second gate electrode has an opening in the portion.

3. The semiconductor memory device according to claim 1, wherein at least the portion comprises a transparent electrode.

4. The semiconductor memory device according to claim 1, wherein the portion overlaps with a channel region of the oxide semiconductor layer.

5. The semiconductor memory device according to claim 1,

wherein the thin film transistor comprises a first resistance value and a second resistance value between the source electrode and the drain electrode when a readout voltage is applied to the first gate electrode,

wherein the second resistance value is changed from the first resistance value when a channel region of the oxide semiconductor layer is exposed to the ultraviolet light, and

wherein the first resistance value is larger than the second resistance value.

6. The semiconductor memory device according to claim 1,

wherein the readout circuit comprises a potential source, an amplifier, and a second thin film transistor,

wherein one of a second source electrode and a second drain electrode of the second thin film transistor is connected to the potential source,

wherein the other of the second source electrode and the second drain electrode are electrically connected to the bit line, and

wherein the amplifier is provided between the other of the second source electrode and the second drain electrode and the one of the source electrode and the drain electrode.

7. The semiconductor memory device according to claim 1,

wherein the thin film transistor comprises a first threshold voltage of a first Id-Vg characteristic and a second threshold voltage of a second Id-Vg characteristic,

wherein the second Id-Vg characteristic is changed from the first Id-Vg characteristic of the thin film transistor exposed to the ultraviolet light, and

wherein the readout voltage is larger than the second threshold voltage and smaller than the first threshold voltage.

8. A semiconductor memory device comprising:

a bit comprising a first thin film transistor and a second thin film transistor;

a row decoder connected to a word line;

a column decoder configured to select a bit line;

a readout circuit electrically connected to the bit line selected by the column decoder;

the first thin film transistor comprising;

a first semiconductor layer;

a first insulating layer over the first semiconductor layer;

a first gate electrode over the first insulating layer; and

a first source electrode and a first drain electrode in electrical contact with the first semiconductor layer;

the second thin film transistor comprising;

a second gate electrode;

a second insulating layer over the second gate electrode;

a second semiconductor layer over the second insulating layer;

wherein the second semiconductor layer comprises an oxide semiconductor layer; and

a second source electrode and a second drain electrode in electrical contact with the second semiconductor layer,

wherein one of the first source electrode and the first drain electrode is connected to one of the second source electrode and the second drain electrode,

wherein the word line is connected to the first gate electrode and the second gate electrode, and

wherein the bit line is connected to any one of the other of the first source electrode and the first drain electrode and the other of the second source electrode and the second drain electrode.

9. The semiconductor memory device according to claim 8, wherein a first channel type of a first electrical characteristic of the first thin film transistor is opposite to a second channel type of a first electrical characteristic of the second thin film transistor.

10. The semiconductor memory device according to claim 8,

wherein the second thin film transistor comprises a first resistance value and a second resistance value between the second source electrode and the second drain electrode when a readout voltage is applied to the second gate electrode,

wherein the second resistance value is changed from the first resistance value when a channel region of the second semiconductor layer is exposed to an ultraviolet light, and

wherein the first resistance value is larger than the second resistance value.

11. The semiconductor memory device according to claim 8,

wherein the readout circuit comprises a potential source, an amplifier, and a third thin film transistor,

wherein one of a third source electrode and a third drain electrode of the third thin film transistor is connected to the potential source,

wherein the other of the third source electrode and the third drain electrode is electrically connected to the bit line, and

wherein the amplifier is provided between the other of the third source electrode and the third drain electrode and any one of the other of the first source electrode and the first drain electrode and the other of the second source electrode and the second drain electrode.

12. The semiconductor memory device according to claim 8,

wherein the first thin film transistor comprises a first threshold voltage of a first Id-Vg characteristic,

wherein the second thin film transistor comprises a second threshold voltage of an second Id-Vg characteristic and a third threshold voltage of a third Id-Vg characteristic,

wherein the third Id-Vg characteristic is changed from the second Id-Vg characteristic of the second thin film transistor exposed to an ultraviolet light, and

wherein the readout voltage is larger than the third threshold voltage and smaller than the first threshold voltage and the second threshold voltage.

13. A semiconductor memory device comprising:

a bit comprising a thin film transistor;

a row decoder connected to a word line;

a column decoder configured to select a bit line;

a readout circuit electrically connected to the bit line selected by the column decoder;

a writing method comprising an ultraviolet light

the thin film transistor comprising;

a first gate electrode;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer over the first insulating layer;

a source electrode and a drain electrode in electrical contact with the oxide semiconductor layer;

a second insulating layer over the source electrode and the drain electrode; and

a second gate electrode over the second insulating layer,

wherein the word line is connected to one of the first gate electrode and the second gate electrode,

wherein the bit line is connected to one of the source electrode and the drain electrode, and

wherein a portion of the other of the first gate electrode and the second gate electrode is capable of transmitting the ultraviolet light when the bit is written by the writing method.

14. The semiconductor memory device according to claim 13, wherein the one of the first gate electrode and the second gate electrode comprises an opening in the portion.

15. The semiconductor memory device according to claim 13, wherein at least the portion comprises a transparent electrode.

16. The semiconductor memory device according to claim 13, wherein the portion overlaps with a channel region of the oxide semiconductor layer.

17. The semiconductor memory device according to claim 13,

wherein the thin film transistor comprises a first resistance value and a second resistance value between the source electrode and the drain electrode when a readout voltage is applied to the first gate electrode,

wherein the second resistance value is changed from the first resistance value when a channel region of the oxide semiconductor layer is exposed to the ultraviolet light, and

wherein the first resistance value is larger than the second resistance value.

18. The semiconductor memory device according to claim 13,

wherein the readout circuit comprises a potential source, an amplifier, and a second thin film transistor,

wherein one of a second source electrode and a second drain electrode of the second thin film transistor is connected to the potential source,

wherein the other of the second source electrode and the second drain electrode are electrically connected to the bit line, and

wherein the amplifier is provided between the other of the second source electrode and the second drain electrode and the one of the source electrode and the drain electrode.

19. The semiconductor memory device according to claim 13,

wherein the thin film transistor comprises a first threshold voltage of an first Id-Vg characteristic and a second threshold voltage of a second Id-Vg characteristic,

wherein the second Id-Vg characteristic is changed from the first Id-Vg characteristic of the thin film transistor exposed to the ultraviolet light, and

wherein the readout voltage is larger than the second threshold voltage and smaller than the first threshold voltage.

20. A semiconductor memory device comprising:

a bit comprising a first thin film transistor and a second thin film transistor;

a row decoder connected to a word line;

a column decoder configured to select a bit line;

a readout circuit electrically connected to the bit line selected by the column decoder;

a writing method comprising an ultraviolet light;

the first thin film transistor comprising;

a first semiconductor layer;

a first insulating layer over the first semiconductor layer;

a first gate electrode over the first insulating layer; and

a first source electrode and a first drain electrode in electrical contact with the first semiconductor layer;

the second thin film transistor comprising;

a second gate electrode;

a second insulating layer over the second gate electrode;

a second semiconductor layer over the second insulating layer;

wherein the second semiconductor layer comprises an oxide semiconductor layer; and

a second source electrode and a second drain electrode in electrical contact with the second semiconductor layer,

wherein one of the first source electrode and the first drain electrode is connected to one of the second source electrode and the second drain electrode,

wherein the word line is connected to the first gate electrode and the second gate electrode,

wherein the bit line is connected to any one of the other of the first source electrode and the first drain electrode and the other of the second source electrode and the second drain electrode,

wherein data are written to the bit by the ultraviolet light from the writing method, and

wherein the data are read by the readout circuit when the bit is selected by the row decoder and the column decoder.

21. The semiconductor memory device according to claim 20, wherein a first channel type of an electrical characteristic of the first thin film transistor is opposite to a second channel type of an electrical characteristic of the second thin film transistor.

22. The semiconductor memory device according to claim 20,

wherein the second thin film transistor comprises a first resistance value and a second resistance value between the second source electrode and the second drain electrode when a readout voltage is applied to the second gate electrode,

wherein the second resistance value is changed from the first resistance value when a channel region of the second semiconductor layer is exposed to the ultraviolet light, and

wherein the first resistance value is larger than the second resistance value.

23. The semiconductor memory device according to claim 20,

wherein the readout circuit comprises a potential source, an amplifier and a third thin film transistor, one of a third source electrode and a third drain electrode of the third thin film transistor is connected to the potential source,

wherein the other of the third source electrode and the third drain electrode is electrically connected to the bit line, and

wherein the amplifier is provided between the other of the third source electrode and the third drain electrode and any one of the other of the first source electrode and the first drain electrode and the other of the second source electrode and the second drain electrode.

24. The semiconductor memory device according to claim 20,

wherein the first thin film transistor comprises a first threshold voltage of a first Id-Vg characteristic, the second thin film transistor comprises a second threshold voltage of an second Id-Vg characteristic and a third threshold voltage of a third Id-Vg characteristic,

wherein the third Id-Vg characteristic is changed from the second Id-Vg characteristic of the second thin film transistor exposed to the ultraviolet light, and

wherein the readout voltage is larger than the third threshold voltage and smaller than the first threshold voltage and the second threshold voltage.