Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride

• US 8,432,719 B2
• Filed: 01/18/2011
• Issued: 04/30/2013
• Est. Priority Date: 01/18/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/008,384
• Publication Number:
  US 20120182807A1
• Time in Patent Office: 833 Days
• Field of Search: 365/130, 365/129, 365/181, 365/173, 365/185.14, 365/185.26
• US Class Current: 365/130
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.

Claims

1. A 3D stacked AND-type flash memory structure, comprising:

a plurality of horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising a plurality of word lines and a plurality of charge trapping multilayers alternately arranged, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between;

a plurality of sets of bit lines and sets of source lines arranged alternately and disposed vertically to the horizontal planes; and

a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, and one set of channels sandwiched between the adjacent sets of bit lines and source lines.

2. The structure according to claim 1, wherein each set of bit lines comprises a plurality of bit line pillars disposed vertically to the horizontal planes.

3. The structure according to claim 2, wherein each set of source lines comprises a plurality of source line pillars disposed vertically to the horizontal planes.

4. The structure according to claim 3, wherein each charge trapping multilayer of each horizontal plane surround the insulation pillars, the bit line pillars and source line pillars, and the channels.

5. The structure according to claim 1, wherein each set of bit lines is disposed between the adjacent set of insulation pillars and the set of channels, while each set of insulation pillars is disposed between the adjacent set of bit lines and set of source lines.

6. The structure according to claim 1, wherein each set of bit lines comprises a plurality of buried bit line portions respectively disposed between the adjacent horizontal planes.

7. The structure according to claim 6, wherein each set of source lines comprises buried source line portions disposed between the adjacent horizontal planes respectively.

8. The structure according to claim 7, wherein each set of channels comprises a plurality of vertical channel regions, and each channel region is sandwiched between the adjacent buried bit line portion and buried source line portion.

9. The structure according to claim 1, wherein the word lines and the sets of channels comprise polysilicon, the sets of insulation pillars comprise oxide, and the sets of bit lines and source lines comprise n-F doped polysilicon.

10. A method for manufacturing 3D stacked AND-type flash memory structure, the method at least comprising:

providing a substrate;

depositing a plurality of gate layers and insulation layers alternately on the substrate;

patterning the gate layers and insulation layers to form a plurality of WL stacks, and each WL stacks comprising alternating patterned gate layers as word lines and patterned insulation layers for isolating the word lines after patterning;

forming a charge-trapping multilayer on the WL stacks, lining the sidewalls of the WL stacks, and forming trenches between the WL stacks lined with the charge-trapping multilayer;

depositing a conductive layer on the WL stacks and filling up the trenches;

patterning the conductive layer to form a plurality of BL stacks, and the BL stacks being spaced apart alternately by a plurality of gaps; and

forming two doped regions at two sides of each BL stack, and a channel vertically sandwiched between the two doped regions, wherein the adjacent BL stacks are isolated from each other.

11. The method according to claim 10, wherein in the step of patterning the conductive layer to form the BL stacks, part of the charge-trapping multilayer is exposed after patterning.

12. The method according to claim 10, wherein the step of forming two doped regions at two sides of each BL stack comprises:

doping two sides of each BL stack and exposed part of the charge-trapping multilayer at the gap between adjacent BL stacks, so as to form two spacers as the bit line and the source line of each BL stack, and form a bottom spacer at the gap between adjacent BL stacks; and

removing the bottom spacer at the gap between adjacent BL stacks to isolate the adjacent BL stacks from each other, wherein the part of the charge-trapping multilayer is exposed after bottom spacer removing.

13. The method according to claim 10, wherein each channel of the BL stack is vertically disposed on the charge-trapping multilayer.

14. The method according to claim 10, wherein the insulation layers are a plurality of oxide layers, and the charge-trapping multilayer is an oxide-nitrite-oxide-nitrite-oxide (ONONO) laminated layer.

15. The method according to claim 10, wherein the two sides of each BL stack are n+ doped regions.

16. The method according to claim 10, wherein the channel sandwiched between the two doped regions is a lightly doped p-type channel.

17. A method for operating 3D stacked AND-type flash memory structure, comprising:

providing a 3D stacked AND-type flash memory structure comprising a plurality of horizontal planes of memory cells arranged in a three-dimensional array, a plurality of sets of bit lines and sets of source lines arranged alternately and disposed vertically to the horizontal planes, and a plurality of sets of channels and sets of insulation pillars arranged alternatively and disposed perpendicularly to the horizontal planes, wherein each horizontal plane comprises a plurality of word lines and a plurality of charge trapping multilayers alternately arranged, and the adjacent word lines are spaced apart from each other with each charge trapping multilayer interposed between, and one set of channels is sandwiched between the adjacent sets of bit lines and source lines;

selecting a memory cell positioned at one of the horizontal planes;

applying an operating voltage to each of two word lines adjacent to the selected memory cell at the horizontal plane to turn on the selected memory cell;

turning off at least one of two channels adjacent to the outsides of said two conducting word lines; and

applying a relative voltage to at least selected one of the sets of bit lines and sets of source lines, and applying 0 voltage to other plural unselected sets of bit lines and unselected sets of source lines.

18. The method according to claim 17, wherein the operating voltages applied to said two word lines adjacent to the selected memory cell are between an erasing voltage and a programming voltage while reading or programming of the selected memory cell is performed.

19. The method according to claim 18, wherein a high negative voltage is applied to each of two selected adjacent set of bit lines and set of source lines, and other unselected sets of bit lines and unselected sets of source lines are applied with 0 voltage while FN programming of the selected memory cell is performed.

20. The method according to claim 17, wherein a negative voltage is applied to each of two channels adjacent to the outsides of said two conducting word lines.

21. The method according to claim 17, wherein plural unselected word lines at the selected horizontal plane having the selected memory cell are applied with 0 voltage or voltages lower than an erasing voltage, to turn off other unselected memory cells.

22. The method according to claim 17, further comprising:

turning off all unselected memory cells positioned at other unselected horizontal planes.

23. The method according to claim 17, further comprising:

applying 0 voltage to all word lines at the horizontal planes, and applying a high positive voltage to each of the sets of bit lines and the sets of source lines for performing a FN erase to all of the memory cells.