Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride
First Claim
1. A 3D stacked AND-type flash memory structure, comprising:
- a plurality of horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising a plurality of word lines and a plurality of charge trapping multilayers alternately arranged, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between;
a plurality of sets of bit lines and sets of source lines arranged alternately and disposed vertically to the horizontal planes; and
a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, and one set of channels sandwiched between the adjacent sets of bit lines and source lines.
1 Assignment
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Accused Products
Abstract
A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.
142 Citations
23 Claims
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1. A 3D stacked AND-type flash memory structure, comprising:
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a plurality of horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising a plurality of word lines and a plurality of charge trapping multilayers alternately arranged, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and sets of source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, and one set of channels sandwiched between the adjacent sets of bit lines and source lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for manufacturing 3D stacked AND-type flash memory structure, the method at least comprising:
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providing a substrate; depositing a plurality of gate layers and insulation layers alternately on the substrate; patterning the gate layers and insulation layers to form a plurality of WL stacks, and each WL stacks comprising alternating patterned gate layers as word lines and patterned insulation layers for isolating the word lines after patterning; forming a charge-trapping multilayer on the WL stacks, lining the sidewalls of the WL stacks, and forming trenches between the WL stacks lined with the charge-trapping multilayer; depositing a conductive layer on the WL stacks and filling up the trenches; patterning the conductive layer to form a plurality of BL stacks, and the BL stacks being spaced apart alternately by a plurality of gaps; and forming two doped regions at two sides of each BL stack, and a channel vertically sandwiched between the two doped regions, wherein the adjacent BL stacks are isolated from each other. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for operating 3D stacked AND-type flash memory structure, comprising:
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providing a 3D stacked AND-type flash memory structure comprising a plurality of horizontal planes of memory cells arranged in a three-dimensional array, a plurality of sets of bit lines and sets of source lines arranged alternately and disposed vertically to the horizontal planes, and a plurality of sets of channels and sets of insulation pillars arranged alternatively and disposed perpendicularly to the horizontal planes, wherein each horizontal plane comprises a plurality of word lines and a plurality of charge trapping multilayers alternately arranged, and the adjacent word lines are spaced apart from each other with each charge trapping multilayer interposed between, and one set of channels is sandwiched between the adjacent sets of bit lines and source lines; selecting a memory cell positioned at one of the horizontal planes; applying an operating voltage to each of two word lines adjacent to the selected memory cell at the horizontal plane to turn on the selected memory cell; turning off at least one of two channels adjacent to the outsides of said two conducting word lines; and applying a relative voltage to at least selected one of the sets of bit lines and sets of source lines, and applying 0 voltage to other plural unselected sets of bit lines and unselected sets of source lines. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification