Invalid write prevention for STT-MRAM array

• US 8,432,727 B2
• Filed: 04/29/2010
• Issued: 04/30/2013
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation, Qualcomm, Inc.
• Original Assignee: Industry-Academic Cooperation Foundation Yonsei University, Qualcomm, Inc.
• Inventors: Ryu, Kyungho, Kim, Jisu, Jung, Seong-Ook, Kang, Seung H.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US12/769,995
• Publication Number:
  US 20110267874A1
• Time in Patent Office: 1,097 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 216/22, 257/295, 257/421, 257/E21.665, 438/3, 428810-816, 428817-8251, 428/826, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.

Claims

1. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

a bit cell array having a first source line substantially parallel to a word line coupled to first bit cells, wherein the first source line is substantially perpendicular to bit lines coupled to the first bit cells; and

a source line control unit coupled to the bit cell array, the source line control unit including a common source line driver coupled to a plurality of source lines including the first source line and a source line selector configured to select individual ones of the plurality of source lines, the source line driver and the source line selector coupled in multiplexed relation.

2. The STT-MRAM of claim 1, further comprising:

a bit line control unit coupled to the bit cell array and the source line control unit, the bit line control unit including a common bit line driver coupled to a plurality of the bit lines and a bit line selector coupled to the plurality of the bit lines, the common bit line driver and the bit line selector in multiplexed relation.

3. The STT-MRAM of claim 2, wherein the bit line control unit includes a plurality of positive channel metal oxide semiconductor (PMOS) elements.

4. The STT-MRAM of claim 2, wherein the bit line control it includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a. plurality of bit line select lines associated with the plurality of bit lines respectively, and each of the plurality of bit lines.

6. The STT-MRAM of claim 1, wherein the source tine control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a plurality of source line select lines associated with the plurality of source lines respectively, and each of the plurality of source lines.

7. The STT-MRAM of claim 1, further comprising:

an invalid write prevention circuit coupled between the bit line control it and the source line control unit.

8. The STT-MRA.M of claim 7, wherein the invalid write prevention circuit includes a positive channel metal oxide semiconductor (PMOS) element.

9. The STT-MRAM of claim 2, further comprising an invalid write prevention circuit configured to set a voltage associated with unselected ones of the plurality of bit lines equal to a selected one of the plurality of source lines.

10. The STT-MRAM of claim 1, integrated in at least one semiconductor die.

11. The STT-MRAM of claim 1, wherein the STT-MRAM is integrated into an electronic device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

5. The STT-MRAM of claim it, wherein the source line control unit includes a plurality of positive channel metal oxide semiconductor (PMOS) elements.