Semiconductor device and method for driving the same

• US 8,432,730 B2
• Filed: 07/19/2011
• Issued: 04/30/2013
• Est. Priority Date: 07/28/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Uochi, Hideki, Kamata, Koichiro
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/185,840
• Publication Number:
  US 20120026787A1
• Time in Patent Office: 651 Days
• Field of Search: 365/163, 257/38
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain.

Claims

1. A semiconductor device comprising:

a transistor including a first gate, a second gate, a third gate and a semiconductor layer; and

a data line electrically connected to the third gate,

wherein the third gate includes an oxide semiconductor,

wherein the semiconductor layer includes a channel formation region,

wherein the first gate overlaps with the channel formation region,

wherein the third gate is provided between the first gate and the channel formation region,

wherein the third gate includes a first region and a second region, the first region overlapping with the channel formation region, and the second region extending beyond an edge of the first gate, and

wherein the second gate overlaps with the second region.

2. The semiconductor device according to claim 1, wherein the semiconductor layer comprises an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein the second gate overlaps with the edge of the first gate, the second region, and an edge of the data line.

8. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a laptop personal computer, a personal digital assistant, an e-book reader, a mobile phone, a digital camera, and a television device.

4. A semiconductor device comprising:

a transistor including a first control gate, a second control gate, a storage gate and a semiconductor layer;

a word line;

a data line;

a control line;

a read signal line; and

a bit line,

wherein the semiconductor layer includes a channel formation region,

wherein the first control gate is electrically connected to the word line,

wherein the second control gate is electrically connected to the control line,

wherein the storage gate is electrically connected to the data line,

wherein one of a source and a drain of the transistor is electrically connected to the read signal line,

wherein the other of the source and the drain is electrically connected to the bit line,

wherein the first control gate overlaps with the channel formation region,

wherein the storage gate is provided between the first control gate and the channel formation region,

wherein the storage gate includes a first region and a second region, the first region overlapping with the channel formation region, and the second region extending beyond an edge of the first control gate, and

wherein the second control gate overlaps with the second region.

5. The semiconductor device according to claim 4, wherein the storage gate comprises an oxide semiconductor.

6. The semiconductor device according to claim 4, wherein the semiconductor layer comprises an oxide semiconductor.

7. The semiconductor device according to claim 4, wherein the second control gate overlaps with the edge of the first control gate, the second region, and an edge of the data line.

9. The semiconductor device according to claim 4, wherein the semiconductor device is one selected from the group consisting of a laptop personal computer, a personal digital assistant, an e-book reader, a mobile phone, a digital camera, and a television device.