Non-volatile memory systems and methods including page read and/or configuration features

• US 8,432,750 B2
• Filed: 12/06/2010
• Issued: 04/30/2013
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, Khan, Sakhawat M.
• Primary Examiner(s): DINH, SON T
• Application Number:
  US12/961,458
• Publication Number:
  US 20110110170A1
• Time in Patent Office: 876 Days
• Field of Search: 365/189.15, 365/189.16, 365/206, 365/207
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Claims

1. A system comprising:

one or more circuits configured to;

read a fuse non-volatile memory location for configuration data in response to a page read command;

store the configuration data in a volatile memory location; and

use the configuration data to initiate a page read sequence for a memory.

2. The system of claim 1 wherein the system is configured to autozero an input and output in order to zero out offset in an amplifier.

3. The system of claim 2 further comprising at least one reference sense amplifier, the system configured to couple inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal.

4. The system of claim 1 further configured to autozero an input and output in order to zero out offset in a reference sense amplifier.

5. The system of claim 4 further comprising a reference sense amplifier, the system configured to capacitively sense an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

6. The system of claim 4 further comprising a reference sense amplifier, the system configured to selectively couple the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

7. The system of claim 1 wherein the system is configured to autozero an input and output in order to zero out offset of reference sense circuitry.

8. The system of claim 1 wherein the system is configured to couple inputs of a reference sense amplifier to an output signal in response to an autozero signal.

9. The system of claim 1 wherein the system is configured to:

operatively couple a reference array to reference memory subarrays; and

provide stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

10. The system of claim 1 wherein the system is configured to set an input and an output of reference circuitry in response to an autozero signal.

11. The system of claim 1 wherein the system is configured to autozero an input and an output in order to zero out an offset of reference circuitry.

12. The system of claim 1 wherein the system is configured to execute a configuration (fuse) bit initialization that loads data from fuse memory cells to volatile latches in a fuse circuit block.

13. The system of claim 1 wherein the system is configured to:

place all data cells in an addressed page into voltage-mode read states;

read cell (reference and data) voltages for the data cells; and

compare read verify voltages with cell read back voltages to determine whether to continue the page read sequence.

14. The system of claim 1 wherein the system is configured to apply an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

15. The system of claim 14 wherein erase blocks include a plurality of pages of memory cells.

16. The system of claim 14 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

17. The system of claim 1 wherein the system is configured to apply a read algorithm programmed via fuses upon one selected page of memory cells at a time.

18. The system of claim 17 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.

19. A system comprising:

one or more circuits configured to;

read a fuse non-volatile memory location for configuration data in response to a page program command;

store the configuration data in a volatile memory location; and

use the configuration data to initiate a page programming sequence for a memory.

20. The system of claim 19 wherein the system is configured to autozero an input and output in order to zero out offset in an amplifier.

21. The system of claim 19 wherein the system is configured to autozero an input and output in order to zero out offset in a reference sense amplifier.

22. The system of claim 21 wherein the system is configured to capacitively sense an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

23. The system of claim 21 wherein the system is configured to selectively couple the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

24. The system of claim 19 wherein the system is configured to autozero an input and output in order to zero out offset of reference sense circuitry.

25. The system of claim 19 wherein the system is configured to couple inputs of a reference sense amplifier to an output signal in response to an autozero signal.

26. The system of claim 19 wherein the system is configured to:

operatively couple a reference array to reference memory subarrays; and

provide stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

27. The system of claim 19 wherein the system is configured to set an input and an output of reference circuitry in response to an autozero signal.

28. The system of claim 19 wherein the system is configured to autozero an input and an output in order to zero out an offset of reference circuitry.

30. The system of claim 19 wherein the system is configured to execute a configuration (fuse) bit initialization that loads data from fuse memory cells to volatile latches in a fuse circuit block.

31. The system of claim 19 wherein the system is configured to compare program verify voltages of cells against data cell read back voltages to indicate whether further programming is required.

32. The system of claim 19 wherein the system is configured to perform the page programming sequence including an iterative verify-program loop, wherein the iterative verify-program loop ends the page programming sequence if a program pulse count reaches a maximum value.

33. The system of claim 32 wherein the iterative verify-program loop determines how many cells have been placed in a program inhibit mode, and further comprising continuing the page programming sequence once the iterative verify-program loop determines that all of the cells have been placed in the program inhibit mode.

34. The system of claim 19 wherein the system is configured to:

perform the page programming sequence including an iterative verify-program loop, wherein the iterative verify-program loop determines how many cells have been placed in a program inhibit mode; and

continue the page programming sequence once the iterative verify-program loop determines that all of the cells have been placed in the program inhibit mode.

35. The system of claim 19 wherein the system is configured to:

generate upper program margin verify voltages; and

compare the upper program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

36. The system of claim 35 further configured to:

generate lower program margin verify voltages; and

compare the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

37. The system of claim 19 wherein the system is configured to:

generate lower program margin verify voltages; and

compare the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

38. The system of claim 19 wherein the system is configured to:

apply an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

39. The system of claim 38 wherein erase blocks include a plurality of pages of memory cells.

40. The system of claim 38 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

41. The system of claim 19 wherein the system is configured to:

apply a read algorithm programmed via fuses upon one selected page of memory cells at a time.

42. The system of claim 41 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.

43. The system of claim 19 wherein the system is configured to:

place all data cells in an addressed page into voltage-mode read states;

read cell (reference and data) voltages for the data cells; and

compare read verify voltages with cell read back voltages to determine whether to continue the page read sequence.

29. The system of 19 wherein the system is configured to:

couple a reference array to reference memory subarrays; and

provide stored reference signals used for programming reference memory cells, the stored reference signals corresponding to detected reference signals.

44. A system comprising:

one or more circuits configured to;

read a fuse non-volatile memory location for configuration data in response to a page read command;

store said configuration data in a volatile memory location; and

provide chip operating settings for a page read sequence for a memory as a function of the configuration data.

45. The system of claim 44 wherein the system is configured to autozero an input and output in order to zero out offset in an amplifier.

46. The system of claim 45 further comprising at least one reference sense amplifier, the system configured to couple inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal.

47. The system of claim 44 further configured to autozero an input and output in order to zero out offset in a reference sense amplifier.

48. The system of claim 47 further comprising a reference sense amplifier, the system configured to capacitively sense an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

49. The system of claim 47 further comprising a reference sense amplifier, the system configured to selectively couple the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

50. The system of claim 44 wherein the system is configured to autozero an input and output in order to zero out offset of reference sense circuitry.

51. The system of claim 44 wherein the system is configured to couple inputs of a reference sense amplifier to an output signal in response to an autozero signal.

52. The system of claim 44 wherein the system is configured to:

operatively couple a reference array to reference memory subarrays; and

provide stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

53. The system of claim 44 wherein the system is configured to set an input and an output of reference circuitry in response to an autozero signal.

54. The system of claim 44 wherein the system is configured to autozero an input and an output in order to zero out an offset of reference circuitry.

55. The system of claim 44 wherein the system is configured to execute a configuration (fuse) bit initialization that loads data from fuse memory cells to volatile latches in a fuse circuit block.

56. The system of claim 44 wherein the system is configured to:

place all data cells in an addressed page into voltage-mode read states;

read cell (reference and data) voltages for the data cells; and

compare read verify voltages with cell read back voltages to determine whether to continue the page read sequence.

57. The system of claim 44 wherein the system is configured to apply an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

58. The system of claim 57 wherein erase blocks include a plurality of pages of memory cells.

59. The system of claim 57 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

60. The system of claim 44 wherein the system is configured to apply a read algorithm programmed via fuses upon one selected page of memory cells at a time.

61. The system of claim 60 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.