Multi-column addressing mode memory system including an integrated circuit memory device

• US 8,432,766 B2
• Filed: 03/01/2012
• Issued: 04/30/2013
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Lai, Lawrence, Bellows, Chad A., Richardson, Wayne S.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/410,254
• Publication Number:
  US 20120170399A1
• Time in Patent Office: 425 Days
• Field of Search: 711/5, 711/105, 711/154, 365/189.04, 365/230.03, 365/230.06, 365/233
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Claims

1. A memory device, comprising:

a request interconnect operable to receive commands from a master device;

first, second, third and fourth storage arrays;

a first data interconnect operable to output data to the master device from the first and third storage arrays;

a second data interconnect operable to output data to the master device from the second and fourth storage arrays;

row access circuitry operable to open a corresponding row in each of the first and fourth storage arrays in response to a first common row access command received at the request interconnect, and to open a corresponding row in each of the second and third storage arrays in response to a second common row access command received at the request interconnect; and

column access circuitry operable to access first data in the opened row in the first storage array according to a first externally-supplied column address, second data in the opened row in the second storage array according to a second externally-supplied column address, third data in the opened row in the third storage array according to a third externally-supplied column address, and fourth data in the opened row in the fourth storage array according to a fourth externally-supplied column address;

where a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to a same open row of storage cells in one of the first, second, third or fourth storage arrays, where the first data and fourth data are output via the respective data interconnects separated by less than the minimum time interval, and where the second data and the third data are output via the respective data interconnects separated by less than the minimum time interval.

2. The memory device of claim 1, embodied as a dynamic random access memory device, where the minimum time interval comprises a T_cc interval.

3. The memory device of claim 1, where the request interconnect is operable to receive in sequence the first common row access command, the second common row access command, a command including the first-externally applied column address, and a command including the third externally-supplied column address, and where the memory device is operable to output the first and third data on a time interleaved basis via the first data interconnect in a manner where the first and third data are separated by less than the minimum time interval.

4. The memory device of claim 3, where

the memory device is operable to concurrently output the first and fourth data respectively via the first and second data interconnects, and to concurrently output the second and third data respectively via the first and second data interconnects;

the memory device is operable to output the second and fourth data on a time interleaved basis via the second data interconnect in a manner where the second and fourth data are separated by less than the minimum time interval; and

the memory device is operable to output the first, second, third and fourth data in a manner separated by not more than twice the minimum time interval.

5. The memory device of claim 4, further comprising dual-column decoder circuitry, the memory device operable to receive the first externally-supplied column address and the fourth externally-supplied column address via a common request packet received by the request interconnect, the memory device operable to receive the second externally-supplied column address and the third externally-supplied column address via a common request packet received by the request interconnect.

6. The memory device of claim 4, embodied as a dynamic random access memory device, where the minimum time interval comprises a T_cc interval.

7. The memory device of claim 1, where each of the first and second data interconnects couple to the respective storage arrays via respectively independent read pipes and respectively independent write pipes.

8. The memory device of claim 7, where each of the first and second data interconnects comprises at least eight parallel signal links.

9. The memory device of claim 8, where each of the at least eight parallel signal links of each of the first and second data interconnects are operable to output data to the master as a respective differential signal.

10. The memory device of claim 1, where the first, second third and fourth storage arrays are arranged in respective quadrants of the memory device, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants.

11. The memory device of claim 10, where the respective quadrants are electrically isolated from one another.

12. The memory device of claim 1, where the first common row access command specifies a first single row address, the opened row in each of the first and fourth storage arrays corresponding to the first single row address, and where the second common row address command specifies a second single row address, the opened-row in each of the second and third arrays corresponding to the second single row address.

13. A memory device, comprising:

first, second, third and fourth storage arrays;

row circuitry operable to activate respective rows in the first and fourth storage arrays in response to a first single row address, and to activate respective rows in the second and third storage arrays in response to a second single row address;

column circuitry operable to access first data in the activated, respective row in the first storage array, second data in the activated, respective row in the second storage array, third data in the activated, respective row in the third storage array, and fourth data in the activated, respective row in the fourth storage array, in response to respective, independent column addresses received at a request interface; and

the memory device operable to time-interleave the output of data from the first storage array and the third storage array for transmission to a master over a first set of external signal links, and to time-interleave the output of data from the second storage array and the fourth storage array for transmission to the master over a second set of external signal links;

where a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to a same open row of storage cells in one of the first, second, third or fourth storage arrays, and where the first data and fourth data are output via the respective sets of signal links separated by less than the minimum time interval, where the second data and the third data are output via the respective sets of signal links separated by less than the minimum time interval.

14. The memory device of claim 13, embodied as a dynamic random access memory device, where the minimum time interval comprises a T_cc interval.

15. The memory device of claim 14, where each of the first and second sets of signal links couple to the respective storage arrays via respectively independent read pipes and respectively independent write pipes.

16. The memory device of claim 13, where the first, second third and fourth storage arrays are arranged in respective quadrants of the memory device, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants.

17. The memory device of claim 13, where the request interface is operable to receive in sequence a first command to activate a first row in the first and fourth storage arrays, the first command identifying the respective first single row address, a second command to activate a second row in the second and third storage arrays, the second command identifying the respective second single row address, a third command identifying the column address to access the first data, and a fourth command identifying the column address to access the third data, and where the memory device is to output the first and third data on a time interleaved basis via the first set of signal links in a manner where the first and third data in a manner separated by less than the minimum time interval.

18. The memory device of claim 17, where

the memory device is operable to concurrently output the first and fourth data via the respective sets of signal links, and to concurrently output the second and third data via the respective sets of signal links;

the memory device is operable to output the second and fourth data on a time interleaved basis via the second set of signal links in a manner where the second and fourth data are separated by less than the minimum time interval; and

the memory device is operable to output the first, second, third and fourth data in a manner separated by not more than twice the minimum time interval.

19. The memory device of claim 17, where:

the memory device further comprises dual-column decoder circuitry;

the third command also identifies the column address to access the fourth data;

the fourth command also identifies the column address to access the second data; and

the dual-column decoder circuitry is operable to decode two column addresses from each of the third command and the fourth command, to responsively access the first, second, third and fourth data in the respective storage arrays.

20. A memory device, comprising:

first, second, third and fourth storage arrays;

a request interface;

means for accessing data in the first and fourth storage arrays responsive to a common row address and respective, independent column addresses, and for outputting the respective data in a manner separated by less time than required to cycle column access circuitry for at least one of the first storage array or the fourth storage array; and

means for accessing data in the second and third storage arrays responsive to a common row address and respective, independent column addresses, and for outputting the respective data in a manner separated by less time than required to cycle column access circuitry for at least one of the second storage array or the third storage array;

where the data from the first and third storage arrays are output via a first data interconnect and the data from the second and third storage arrays are output via a second data interconnect.

21. A memory device, comprising:

first, second, third and fourth storage arrays;

a request interconnect;

circuitry operable to access data in the first and fourth storage arrays responsive to a first common row address and respective, independent column addresses, and to output the respective data in a manner separated by less time than required to cycle column access circuitry for at least one of the first storage array or the fourth storage array; and

circuitry operable to access data in the second and third storage arrays responsive to a second common row address and respective, independent column addresses, and to output the respective data in a manner separated by less time than required to cycle column access circuitry for at least one of the second storage array or the third storage array;

where the data from the first and third storage arrays are output via a first data interconnect and the data from the second and third storage arrays are output via a second data interconnect.

22. The memory device of claim 21, embodied as a dynamic random access memory device, where the time required to cycle column access circuitry comprises a T_cc interval.

23. The memory device of claim 21, where the first, second third and fourth storage arrays are arranged in respective quadrants of the memory device, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants.

24. The memory device of claim 23, where each of the first and second data interconnects couple to the respective storage arrays via respectively independent read pipes and respectively independent write pipes.

25. The memory device of claim 23, where the request interface is operable to receive in sequence a first command to activate a first row in each of the first and fourth storage arrays according to the first common row address, a second command to activate a second row in the second and third storage arrays according to the second common row address, a third command identifying the independent column address for the first storage array, and a fourth command identifying the independent column address to access the third storage array, and where the memory device is to output the respective data from the first and third storage arrays on a time interleaved basis via the first data interconnect in a manner separated by less than the minimum time interval.

26. The memory device of claim 25, where

the memory device is operable to concurrently output the data from the first and fourth storage arrays via the respective first and second data interconnects, and to concurrently output the data from the second and third storage arrays via the respective second and first data interconnects;

the memory device is operable to output the data from the second and fourth storage arrays on a time interleaved basis via the second data interconnect, separated by less than the minimum time interval; and

the memory device is operable to output the data from the first, second, third and fourth storage arrays in a manner separated by not more than twice the minimum time interval.

27. The memory device of claim 25, where:

the memory device further comprises dual-column decoder circuitry;

the third command also identifies the independent column address for the fourth storage array;

the fourth command also identifies the independent column address to access the second storage array data; and

the dual-column decoder circuitry is operable to decode two column addresses from each of the third command and the fourth command, to responsively access the data from the respective first, second, third and fourth storage arrays.

28. A memory device, comprising:

a request interconnect to receive commands from a master device;

first, second, third and fourth storage arrays of dynamic random access memory (DRAM) cells, the first and fourth storage arrays operable to store respective first and second halves of first pages of data, the second and third storage arrays operable to store respective first and second halves of second pages of data;

a first data interconnect operable to interleave data from the first halves of the first and second pages for output to a master, and a second data interconnect operable to interleave data from the second halves of the first and second pages for output to a master;

circuitry operable to sense one of the first pages of data in the first and fourth storage arrays in response to a first row address received via the request interconnect, and to sense one of the second pages of data in the second and third storage arrays in response to a second row address received via the request interconnect;

column access circuitry operable to access independent columns of data in the respective halves of the sensed one of the first pages of data responsive to respective column addresses received via the request interconnect, to concurrently output said accessed independent columns of data from the sensed one of the first pages via the respective first and second data interconnects, to access independent columns in the respective halves of the sensed one of the second pages of data responsive to respective column addresses received via the request interconnect, and to concurrently output said accessed independent columns of data from the sensed one of the second pages via the respective first and second data interconnects.

29. The memory device of claim 28, where the first, second third and fourth storage arrays are arranged in respective quadrants of the memory device, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants.