Mesochronous signaling system with multiple power modes

• US 8,432,768 B2
• Filed: 07/09/2009
• Issued: 04/30/2013
• Est. Priority Date: 01/12/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Palmer, Robert E., Poulton, John W.
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/132,104
• Publication Number:
  US 20110235764A1
• Time in Patent Office: 1,391 Days
• Field of Search: 365/189.011, 365/189.17, 365/191, 365/233.1, 365/233.11
• US Class Current: 365/233.1
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 12/0857 by multiple requestors
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 : Control signal input circuits
• CPC Class Codes: G11C 7/1093 : Input synchronization
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Claims

1. An integrated-circuit memory device comprising:

a clock receiver to receive a first clock signal via a clock input;

a signaling circuit to receive the first clock signal from the clock receiver and to output a data signal conveying data bits from the integrated-circuit memory device in response to transitions of the first clock signal, the first clock signal having a respective transition for each bit of data conveyed in the data signal, wherein each bit of data conveyed in the data signal is valid at an output of the integrated-circuit memory device for a respective bit time, and wherein a phase offset between the data signal at the output of the integrated-circuit memory device and the first clock signal at the clock input is permitted to drift by at least the bit time; and

control circuitry to disable operation of the clock receiver in response to a control signal from a memory controller.

2. The integrated-circuit memory device of claim 1 wherein the first clock signal is received from the memory controller.

3. The integrated-circuit memory device of claim 1 further comprising a command signal receiver to receive one or more command signals conveying memory access requests from the memory controller to the memory device, wherein the circuitry to disable operation of the clock receiver in response to the control signal from the memory controller comprises circuitry to disable operation of the command signal receiver in response to the control signal.

4. The integrated-circuit memory device of claim 1 wherein the clock receiver comprises a current source to establish a bias current, and wherein the control circuitry comprises circuitry to disable flow of the bias current.

5. The integrated-circuit memory device of claim 1 further comprising:

a plurality of receivers to receive respective data signals received via a plurality of data links; and

wherein the control circuitry comprises circuitry to render the receivers into a reduced power mode during a first interval in which no data signals are to be received via the data links.

6. The integrated-circuit memory device of claim 5 further comprising:

a plurality of transmitters to output respective data signals via the plurality of data links, the plurality of transmitters including the signaling circuit to receive the first clock signal from the clock receiver and to output a data signal; and

wherein the control circuitry comprises circuitry to render the transmitters into a reduced power mode during a second interval in which not data signals are to be output via the data links.

7. The integrated-circuit memory device of claim 5 wherein the control circuitry comprises circuitry to disable a bias current within the receivers to render the receivers into a reduced power mode during the first interval.

8. The memory device of claim 5 further comprising a command interface to receive memory access commands including (i) memory write commands that indicate corresponding intervals in which data signals are to be received within the memory device via the data links and amplified within the receivers, and (ii) memory read commands that indicate corresponding intervals in which data signals are to be amplified within the transmitters and output from the memory device via the data links.

9. The memory device of claim 8 wherein the control circuitry to render the receivers into a reduced power mode during a first interval comprises circuitry to render the receivers into a reduced power mode upon determining that no memory write command corresponding to the first interval has been received.

10. The memory device of claim 9 wherein the control circuitry to render the transmitters into a reduced power mode during a second interval comprises circuitry to render the transmitters into the reduced power mode upon determining that no memory read command corresponding to the second interval has been received.

11. A memory controller comprising:

driver circuitry to output a first timing signal to a memory device, the first timing signal to time transmission of a data signal conveying data bits from the memory device to the memory controller and having a respective transition for each bit of data conveyed in the data signal;

control circuitry to disable toggling of the first timing signal during an idle period between memory access operations to reduce power consumption within the memory device; and

wherein each bit of data conveyed in the data signal is valid at an output of the memory device for a respective bit time, and wherein a phase offset between the data signal and the first timing signal is permitted to drift by at least the bit time.

12. The memory controller of claim 11 wherein the control circuitry comprises circuitry to render data signal receive circuitry of the memory device into a reduced power mode during a first interval in which no data signals are to be received within the memory device and to render data signal transmit circuitry into a reduced power mode during a second interval in which no data signals are to be output from the memory device.

13. The memory controller of claim 11 wherein the first timing signal is a clock signal.

14. The memory controller of claim 11 further comprising:

a timing signal generator to generate the first timing signal and a second timing signal; and

a data signal receiver to receive the data signal in response to transitions of the second timing signal.

15. The memory controller of claim 14 wherein the timing signal generator comprises a frequency-divider circuit coupled to receive the second timing signal, the frequency-divider circuit to frequency-divide the second timing signal to produce the first timing signal.

16. A method of operation within an integrated-circuit memory device, the method comprising:

receiving a first clock signal via a clock input of the integrated-circuit memory device;

outputting a data signal conveying data bits from the integrated-circuit memory device in response to transitions of the first clock signal, the first clock signal having a respective transition for each bit of data conveyed in the data signal, wherein each bit of data conveyed in the data signal is valid at an output of the integrated-circuit memory device for a respective bit time, and wherein a phase offset between the data signal at the output of the integrated-circuit memory device and the first clock signal at the clock input of the integrated circuit memory device is permitted to drift by at least the bit time; and

disabling reception of the first clock signal in response to a control signal from a memory control component.

17. The method of claim 16 wherein receiving the first clock signal via the clock input comprises receiving the first clock signal from the memory control component.

18. The method of claim 16 further comprising receiving, via a command signal receiver, one or more command signals conveying memory access requests from the memory control component to the memory device, and disabling operation of the command signal receiver in response to the control signal.

19. The method of claim 16 wherein receiving the first clock signal comprises receiving the first clock signal via a clock signal receiver, and wherein disabling reception of the first clock signal comprises disabling a power source within the clock signal receiver.

20. The method of claim 16 further comprising:

receiving data signals within a plurality of data signal receivers via a respective plurality of data links; and

rendering the data signal receivers into a reduced power mode during a first interval in which no data signals are to be received via the data links.

21. The method of claim 20 wherein outputting the data signal from the integrated-circuit memory device in response to transitions of the first clock signal comprises outputting the data signal via one of the data links from a transmitter circuit, the method further comprising rendering the transmitter circuit into a reduced power mode during a second interval in which no data signals are to be output via the data links.

22. The method of claim 20 wherein rendering the data signal receivers into a reduced power mode comprises disabling a power source within the data signal receivers during the first interval.

23. The method of claim 20 further comprising receiving memory access commands including (i) memory write commands that indicate corresponding intervals in which data signals are to be received within the memory device via the data links, and (ii) memory read commands that indicate corresponding intervals in which data signals are to be output from the memory device via the data links.

24. The method of claim 23 wherein rendering the data signal receivers into the reduced power mode during a first interval comprises rendering the data signal receivers into the reduced power mode in response to determining that no memory write command corresponding to the first interval has been received.

25. The method of claim 24 wherein rendering the transmitter circuit into the reduced power mode during the second interval comprises rendering the transmitter circuit into the reduced power mode in response to determining that no memory read command corresponding to the second interval has been received.