Arrangement for utilization rate display and methods thereof

• US 8,432,827 B2
• Filed: 03/07/2011
• Issued: 04/30/2013
• Est. Priority Date: 08/07/2007
• Status: Active Grant

• Current Assignee: Keysight Technologies Singapore (Holdings) Pte. Limited. (Keysight Technologies, Inc.)
• Original Assignee: Net Optics Incorporated (Keysight Technologies, Inc.)
• Inventors: Matityahu, Eldad, Shaw, Robert, Carpio, Dennis Angelo Ramirez, Le, Ky Hong, Lee, Dong Su
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): FARAHMAND, ASHIL S
• Application Number:
  US13/042,135
• Publication Number:
  US 20110164521A1
• Time in Patent Office: 785 Days
• Field of Search: 709/224, 370/252
• US Class Current: 370/252
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 43/045 for graphical visualisation of monitoring data
• CPC Class Codes: H04L 43/0876 Network utilisation, e.g. volume of load or congestion level
• CPC Class Codes: H04L 43/12 Network monitoring probes

Abstract

A network arrangement for automatically displaying statistical data is provided. The arrangement includes a port for receiving data traffic, a physical interface layer for copying data traffic, and a bus for directing a copy of the data traffic to monitoring devices. The arrangement also includes logic arrangement for analyzing the copy of data traffic, which includes at least a Receive Data Valid signal (including a rising edge and a falling edge) and a Receive Clock signal (including a rising edge and a falling edge). The arrangement further includes incrementing a first counter when the Receive Data Valid rising edge is received and incrementing a second counter when at least one of the Receive Clock rising edge and the Receive Clock falling edge is received. The arrangement moreover includes logic arrangement for displaying statistical data pertaining to the data traffic and a visual display arrangement for displaying statistical data.

Claims

1. A network arrangement for automatically displaying statistical data on a network device, comprising:

a set of input ports for receiving data traffic, wherein said set of input ports including at least a first port;

a physical interface layer (PHY) configured for copying said data traffic;

a bus configured for directing a copy of said data traffic to a set of monitoring devices;

a first logic arrangement for analyzing said copy of said data traffic, wherein said data traffic including a plurality of signals, wherein said plurality of signals including at least

a Receive Data Valid signal, wherein said Receive Data Valid signal including a Receive Data Valid rising edge and a Receive Data Valid falling edge, and

a Receive Clock signal, wherein said Receive Clock signal including a Receive Clock rising edge and a Receive Clock falling edge, said Receive Clock rising edge being a first byte of data and said Receive Clock falling edge being a second byte of data;

a first counter configured to be incremented by one when said Receive Data Valid rising edge is received, said Receive Data Valid rising edge indicating a valid data packet;

a second counter configured to be incremented by one when at least one of said Receive Clock rising edge and said Receive Clock falling edge is received;

a second logic arrangement for displaying said statistical data pertaining to said data traffic; and

a visual display arrangement being configured to display said statistical data.

2. The network arrangement of claim 1 wherein said bus is a reduced gigabit media independent interface (RGMII).

3. The network arrangement of claim 2 wherein said first logic arrangement includes a field-programmable field array (FPGA).

4. The network arrangement of claim 3 wherein said FPGA is configured to perform analysis of said Receive Data Valid signal and said Receive Clock signal to determine a utilization rate of said network device, said utilization rate being said network device throughput.

5. The network arrangement of claim 4 wherein said Receive Clock is a 125 megahertz clock with a double rate transmission.

6. The network arrangement of claim 5 wherein said FPGA is configured to correlate said Receive Data Valid signal to said Receive Clock signal to determine number of bytes in said valid data packet.

7. The network arrangement of claim 6 wherein said number of bytes in said valid data packet is received by a microprocessor, said microprocessor including logic to perform calculations on data gathered by said FPGA to generate said statistical data, said logic including

converting said number of bytes to a number of bits,

normalizing said number of bits, and

calculating said utilization rate by dividing said number of bits by maximum line rate for said network device.

8. The network arrangement of claim 1 wherein said visual display arrangement is an LCD (liquid crystal display) screen.

9. The network arrangement of claim 8 wherein said statistical data displayed on said visual display arrangement is configured to be cycled through.

10. The network arrangement of claim 9 wherein said statistical data is displayed for a pre-set time period.

11. The network arrangement of claim 10 wherein said statistical data is displayed in a text format.

12. The network arrangement of claim 10 wherein said statistical data is displayed in a graphic format.

13. A method for automatically displaying statistical data on a visual display arrangement of a network device, comprising:

receiving a first data packet at a first port of a set of input network ports, wherein said first port including a first counter and a second counter;

copying said first data packet;

utilizing a bus to direct a copy of said first data packet to a set of monitoring devices, wherein said bus is associated with said first port;

extracting a plurality of signals from said bus, wherein said plurality of signals including at least

a Receive Data Valid signal, wherein said Receive Data Valid signal including a Receive Data Valid rising edge and a Receive Data Valid falling edge, and

a Receive Clock signal, wherein said Receive Clock signal including a Receive Clock rising edge and a Receive Clock falling edge, said Receive Clock rising edge being a first byte of data and said Receive Clock falling edge being a second byte of data;

incrementing said first counter by one when said Receive Data Valid rising edge is received, said Receive Data Valid rising edge indicating a valid data packet;

incrementing said second counter by one when at least one of said Receive Clock rising edge and said Receive Clock falling edge is received;

correlating data collected by said first counter and said second counter to calculate said statistical data; and

displaying said statistical data on said visual display arrangement of said network device.

14. The method of claim 13 wherein said bus is a reduced gigabit media independent interface (RGMII).

18. The method of claim 13 wherein said visual display arrangement is an LCD (liquid crystal display) screen.

19. The method of claim 13 wherein displaying said statistical data includes periodically updating said statistical data to display real-time data.

20. The method of claim 13 wherein displaying said statistical data includes utilizing a cycling method wherein portion of said statistical data is displayed for a pre-set time period.

21. The method of claim 13 wherein displaying said statistical data includes displaying said statistical data as one of a text format and a graphic format.

15. The method of 14 wherein a field-programmable field array (FPGA) is configured to perform analysis of said Receive Data Valid signal and said Receive Clock signal to determine a utilization rate of said network device, said utilization rate being said network device throughput.

16. The method of claim 15 wherein said FPGA is configured to correlate said Receive Data Valid signal to said Receive Clock signal to determine number of bytes in said valid data packet.

17. The method of claim 16 wherein said number of bytes in said valid data packet is received by a microprocessor, said microprocessor including logic to perform calculations on data gathered by said FPGA to generate said statistical data, said logic including

converting said number of bytes to a number of bits,

normalizing said number of bits, and

calculating said utilization rate by dividing said number of bits by maximum line rate for said network device.