High-speed serial data transceiver and related methods

• US 8,433,020 B2
• Filed: 06/05/2006
• Issued: 04/30/2013
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Buchwald, Aaron W., Le, Michael, Van Engelen, Josephus, Jiang, Xicheng, Wang, Hui, Baumer, Howard A., Madisetti, Avanindra
• Primary Examiner(s): Puente, Eva
• Application Number:
  US11/446,144
• Publication Number:
  US 20060227917A1
• Time in Patent Office: 2,521 Days
• Field of Search: 375/355, 375/354, 375/369, 375/371, 375/359, 375/260, 375/368, 370/516, 327/244, 327/158, 327/156, 327/277, 327/292, 713/600, 713/400
• US Class Current: 375/355
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Claims

1. A method for sampling a high data rate signal in a communication device, comprising:

sampling a received serial data signal using each of a plurality of time-staggered sampling signals to generate a plurality of time-staggered sampled signals;

time-deskewing said plurality of time-staggered sampled signals to generate a plurality of time-deskewed sampled signals, wherein said time-deskewing comprises removing time offsets between said plurality of time-staggered sampled signals, said time offsets representing a difference between said time-staggered sampling signals and said received serial data signal;

generating a parallel signal from said time-deskewed sampled signals, wherein said parallel signal includes samples of said received serial data signal; and

adjusting said plurality of time-staggered sampling signals based on said time offsets.

2. The method of claim 1, wherein said received serial data signal is an analog data signal having a multi-gigabit data rate.

3. The method of claim 2, wherein each of said time-staggered sampled signals has a data rate lower than said multi-gigabit data rate.

4. The method of claim 1, wherein said parallel signal has a data rate substantially equal to said multi-gigabit data rate.

5. The method of claim 1, wherein adjusting said plurality of time-staggered sampling signals comprises:

adjusting said plurality of time-staggered sampling signals such that each of said time-staggered sampling signals has an interpolated phase.

6. The method of claim 1, wherein adjusting said plurality of time-staggered sampling signals comprises:

adjusting said plurality of time-staggered sampling signals based on a timing signal;

generating a set of reference signals having different phases from said timing signal;

generating a second timing signal having an interpolated phase from said set of reference signals; and

adjusting said plurality of time-staggered sampling signals based on said second timing signal, wherein each of said plurality of time-staggered sampling signals has an interpolated phase related to said interpolated phase of said second timing signal.

7. The method of claim 1, wherein said sampling the received serial data signal comprises:

sampling said received serial data signal at a plurality of sampling times, each of said plurality of sampling times corresponding to a respective one of said plurality of time-staggered sampling signals.

8. A communication device, comprising:

means for sampling a received serial data signal using each of a plurality of time-staggered sampling signals to generate a plurality of time-staggered sampled signals;

means for time-deskewing said plurality of time-staggered sampled signals to generate a plurality of time-deskewed sampled signals, wherein said means for time-deskewing removing time offsets between said plurality of time-staggered sampled signals, said time offsets representing a difference between said time-staggered sampling signals and said received serial data signal;

means for generating a parallel signal from said time-deskewed sampled signals, wherein said parallel signal includes samples of said received serial data signal; and

means for adjusting said plurality of time-staggered sampling signals based on said time offsets.

9. The communication device of claim 8, wherein said received serial data signal is an analog data signal having a multi-gigabit data rate.

10. The communication device of claim 9, wherein each of said time-staggered sampled signals has a data rate lower than said multi-gigabit data rate.

11. The communication device of claim 8, wherein said parallel signal has a data rate substantially equal to said multi-gigabit data rate.

12. The communication device of claim 8, wherein said means for adjusting said plurality of time-staggered sampling signals comprises:

means for adjusting said plurality of time-staggered sampling signals such that each of said sampling signals has an interpolated phase.

13. The communication device of claim 8, wherein said means for adjusting said plurality of time-staggered sampling, signals comprises:

means for generating a plurality of time-staggered sampling signals based on a timing signal;

means for generating a set of reference signals having different phases from said timing signal;

means for generating a second timing signal having an interpolated phase from said set of reference signals; and

means for adjusting said plurality of time-staggered sampling signals from said second timing signal, wherein each of said plurality of time-staggered sampling signals has an interpolated phase related to said interpolated phase of said second timing signal.

14. The communication device of claim 8, wherein said means for sampling a received serial data signal comprises:

means for sampling said received serial data signal at a plurality of sampling times, each of said plurality of sampling times corresponding to a respective one of said plurality of time-staggered sampling signals.

16. The communication device of claim 14, wherein said received serial data signal is an analog data signal having a multi-gigabit data rate.

17. The communication device of claim 16, wherein each of said time-staggered sampled signals has a data rate lower than said multi-gigabit data rate.

15. A communication device, comprising:

a sampler that comprises a plurality of sampling paths, each sampling path being configured to sample a received serial data signal using a corresponding one of a plurality of time-staggered sampling signals, thereby generating a plurality of time-staggered sampled signals;

a time-deskewer configured to time-deskew said time-staggered sampled signals to generate a plurality of time-deskewed sampled signals, wherein said time-deskewed sampling signals are characterized as having approximately zero time offset relative to one another, said time offset representing a difference between said time-staggered sampling signals and said received serial data signal;

a deserializer configured to generate a parallel signal from said time-deskewed sampled signals, wherein said parallel signal includes samples of said received serial data signal; and

a sampling signal generator configured to adjust said plurality of time-staggered sampling signals based on a plurality of time offsets removed from said time-staggered sampled signals by said time-deskewer.

18. The communication device of claim 15, wherein said parallel signal has a data rate substantially equal to said multi-gigabit data rate.

19. The communication device of claim 15, wherein said sampling signal generator is further configured to generate said plurality of time-staggered sampling signals based on a timing signal, and wherein said sampling signal generator comprises:

a signal generator configured to generate a set of reference signals having different phases from said timing signal; and

a phase interpolator module configured to generate a second timing signal having an interpolated phase from said set of reference signals and to adjust said plurality of time-staggered sampling signals from said second timing signal, wherein each of said plurality of time-staggered sampling signals has an interpolated phase related to said interpolated phase of said second timing signal.

20. The communication device of claim 15, wherein each of said plurality of sampling paths comprises:

a quantizer configured to quantize a corresponding one of said plurality of time-staggered sampled signals.

21. A communication device, comprising:

a sampler that comprises a plurality of sampling paths, each sampling path being configured to sample a received serial data signal using a corresponding one of a plurality of time-staggered sampling signals, thereby generating a plurality of time-staggered sampled signals;

a time-deskewer configured to time-deskew said time-staggered sampled signals to generate a plurality of time-deskewed sampled signals, wherein said time-deskewer is configured to remove time offsets between said plurality of time-staggered sampled signals, said time offsets representing a difference between said time-staggered sampling signals and said received serial data signal;

a deserializer configured to generate a parallel signal from said time-deskewed sampled signals, wherein said parallel signal includes samples of said received serial data signal; and

a sampling signal generator configured to adjust said plurality of time-staggered sampling signals based on said time offsets.