Digital phase-locked loop with gated time-to-digital converter
First Claim
1. An apparatus comprising:
- a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and
a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to generate the enable signal based solely on the main reference signal.
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Abstract
A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
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Citations
22 Claims
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1. An apparatus comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to generate the enable signal based solely on the main reference signal. - View Dependent Claims (2, 3, 4)
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5. An apparatus comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to delay the main reference signal to obtain a second reference signal, and to generate the enable signal based on the main reference signal and the second reference signal. - View Dependent Claims (6, 7)
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8. An apparatus comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal; and a radio frequency (RF) accumulator configured to receive a main clock signal and count number of cycles of the main clock signal, wherein the RF accumulator and the TDC are part of a digital phase-locked loop (DPLL), and wherein the RF accumulator is enabled when the DPLL is not locked and is disabled after the DPLL has locked.
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9. An integrated circuit comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to generate the enable signal based solely on the main reference signal.
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10. An integrated circuit comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to delay the main reference signal to obtain a second reference signal, and to generate the enable signal based on the main reference signal and the second reference signal. - View Dependent Claims (11, 12)
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13. An integrated circuit comprising:
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a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to gate a main clock signal with the enable signal to obtain the first clock signal, the main clock signal being continuous, and the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time.
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14. A wireless device comprising:
a digital phase-locked loop (DPLL) comprising; a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal, wherein the control unit is configured to generate the enable signal based solely on the main reference signal.
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15. A wireless device comprising:
a digital phase-locked loop (DPLL) comprising; a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal; and a radio frequency (RE) accumulator configured to receive a main clock signal and count number of cycles of the main clock signal, the RF accumulator being enabled when the DPLL is not locked and being disabled after the DPLL has locked.
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16. A wireless device comprising:
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a digital phase-locked loop (DPLL) comprising; a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal; a first modulation path configured to process a modulating signal and provide an input phase signal; and a second modulation path configured to process the modulating signal and provide a scaled modulating signal, and wherein the input phase signal is applied prior to a loop filter and the scaled modulating signal is applied after the loop filter.
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17. A method implemented in a wireless device, the method comprising:
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receiving a first clock signal and a first reference signal at a time-to-digital converter (TDC); providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; generating an enable signal based solely on a main reference signal; and enabling and disabling the TDC based on the enable signal.
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18. A method implemented in a wireless device, the method comprising:
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receiving a first clock signal and a first reference signal at a time-to-digital converter (TDC); providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; generating an enable signal based on a main reference signal; enabling and disabling the TDC based on the enable signal; delaying the main reference signal to obtain a second reference signal; and generating the enable signal based on the main reference signal and the second reference signal.
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19. An apparatus comprising:
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time-to-digital converter (TDC) means for receiving a first clock signal and a first reference signal; means for providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; means for generating an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal; RF accumulator means for receiving a main clock signal and count number of cycles of the main clock signal, wherein the RF accumulator means and the TDC means are part of a digital phase-locked loop (DPLL); means for enabling the RF accumulator means when the DPLL is not locked; and means for disabling the RF accumulator means after the DPLL has locked.
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20. An integrated circuit comprising:
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time-to-digital converter (TDC) means for receiving a first clock signal and a first reference signal; means for providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; means for generating an enable signal based on a main reference signal; and means for enabling and disabling the TDC means based on the enable signal; gating a main clock signal with the enable signal to obtain the first clock signal, the main clock signal being continuous, and the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time.
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21. A non-transitory computer readable storage medium comprising instructions that, when executed by a processor, perform a method comprising:
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receiving a first clock signal and a first reference signal at a time-to-digital converter (TDC); providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; generating an enable signal based solely on a main reference signal; and enabling and disabling the TDC based on the enable signal.
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22. A non-transitory computer readable storage medium comprising instructions that, when executed by a processor, perform a method comprising:
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receiving a first clock signal and a first reference signal at a time-to-digital converter (TDC); providing a TDC output indicative of a phase difference between the first clock signal and the first reference signal; generating an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal; receiving a main clock signal and count number of cycles of the main clock signal at an RF accumulator, wherein the RF accumulator and the TDC are part of a digital phase-locked loop (DPLL); enabling the RF accumulator when the DPLL is not locked; and disabling the RF accumulator after the DPLL has locked.
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Specification