One-time programmable memories for key storage

• US 8,433,930 B1
• Filed: 09/17/2010
• Issued: 04/30/2013
• Est. Priority Date: 01/25/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Joyce, Juju, Langhammer, Martin, Streicher, Keone, Jefferson, David
• Primary Examiner(s): Gee, Jason
• Application Number:
  US12/884,753
• Time in Patent Office: 956 Days
• Field of Search: 719/173, 713/193
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/16 Obfuscation or hiding, e.g. involving white box
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.

Claims

1. An integrated circuit comprising:

an obfuscation circuit;

a memory coupled to the obfuscation circuit;

a reverse obfuscation circuit coupled to the memory;

a first circuit coupled to the memory;

a write enable line coupling the first circuit to the memory;

a second circuit coupled to the first circuit, wherein the second circuit is configured to disable the first circuit after a key is written to the memory; and

a third circuit configured to;

prevent the memory from outputting the key written to the memory when the first circuit is enabled; and

allow the memory to output the key written to the memory when the first circuit is disabled.

2. The integrated circuit of claim 1 wherein the memory is selected from the group consisting of Flash, electrically erasable programmable read-only memory, erasable programmable read-only memory, dynamic random-access memory, and a static random-access memory.

3. The integrated circuit of claim 1 wherein the memory comprises a one time programmable element.

4. The integrated circuit of claim 1 wherein the second circuit comprises a programmable connection.

5. The integrated circuit of claim 1 further comprising:

a decoding circuit coupled to the reverse obfuscation circuit,

wherein the decoding circuit receives a recovered key, and uses the recovered key to decode an encoded configuration bitstream.

6. The integrated circuit of claim 1 wherein the integrated circuit is a field programmable gate array.

7. A method comprising:

writing a key to a memory, wherein;

a first circuitry is coupled to the memory by a write enable line, and

the first circuitry is enabled during the writing of the key to the memory;

preventing the memory from outputting the key written to the memory when the first circuitry is enabled;

allowing the memory to output the key written to the memory when the first circuitry is disabled; and

disabling the first circuitry using second circuitry after the key is written to the memory.

8. The method of claim 7 further comprising:

obfuscating the key with obfuscation circuitry prior to the writing of the key to the memory;

reading the key from the memory; and

recovering the key read from the memory with reverse obfuscation circuitry.

9. The method of claim 7 wherein the memory is selected from the group consisting of Flash, electrically erasable programmable read-only memory, erasable programmable read-only memory, dynamic random-access memory, and a static random-access memory.

10. The integrated circuit of claim 7 wherein the memory comprises a one time programmable element.

11. The integrated circuit of claim 7 wherein the first circuitry comprises a programmable connection.

12. The integrated circuit of claim 8 further comprising:

using the recovered key to decode an encoded configuration bitstream.

13. The method of claim 7, wherein the first circuitry and the second circuitry are implemented on a field programmable gate array.

14. An integrated circuit comprising:

a memory;

input circuitry configured to write a key to the memory;

first circuitry coupled to the memory by a write enable line, wherein the first circuitry is enabled during the writing of the key to the memory;

control circuitry configured to;

prevent the memory from outputting the key written to the memory when the first circuitry is enabled; and

allow the memory to output the key written to the memory when the first circuitry is disabled; and

second circuitry coupled to the first circuitry, wherein the first circuitry is configured to disable the first circuitry using after the key is written to the memory.

15. The integrated circuit of claim 14 further comprising:

obfuscation circuitry configured to obfuscate the key with prior to the writing of the key to the memory;

output circuitry configured to read the key from the memory; and

reverse obfuscation circuitry configured to recover the key read from the memory.

16. The integrated circuit of claim 14 wherein the memory is selected from the group consisting of Flash, electrically erasable programmable read-only memory, erasable programmable read-only memory, dynamic random-access memory, and a static random-access memory.

17. The integrated circuit of claim 14 wherein the memory comprises a one time programmable element.

18. The integrated circuit of claim 14 wherein the second circuit comprises a programmable connection.

19. The integrated circuit of claim 15 further comprising:

a decoding circuit coupled to the reverse obfuscation circuit,

wherein the decoding circuit receives a recovered key, and uses the recovered key to decode an encoded configuration bitstream.

20. The integrated circuit of claim 14 wherein the integrated circuit is a field programmable gate array.