Data processing apparatus and method for testing a circuit block using scan chains

• US 8,433,961 B2
• Filed: 05/06/2010
• Issued: 04/30/2013
• Est. Priority Date: 05/06/2010
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Hughes, Paul Stanley
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US12/662,856
• Publication Number:
  US 20110276848A1
• Time in Patent Office: 1,090 Days
• Field of Search: 714/715, 714/724, 714726-729, 714732-734, 714/738, 714/742
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning

Abstract

A data processing apparatus comprises a circuit block to be tested, and a plurality of scan chains, each scan chain providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation. Configurable decompression circuitry is provided for supporting a plurality of decompression schemes associated with more than one test generation tool, and configuration circuitry is responsive to a configuration stimulus to configure the configurable decompression circuitry to implement a selected decompression scheme. Thereafter, on receipt of compressed input test data, the configurable decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to the plurality of scan chains. Configurable compression circuitry can also be provided in a similar manner, with the configuration stimulus being used to configure the configurable compression circuitry to implement a selected compression scheme to be applied to the output test data in order to produce compressed output test data to be issued from an output interface. Such a mechanism provides a particularly flexible approach for supporting compression and decompression schemes in association with the data input to, and output from, the plurality of scan chains.

Claims

1. A data processing apparatus comprising:

a circuit block to be tested;

a plurality of scan chains, each scan chain in said plurality providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation;

an input interface for receiving compressed input test data;

decompression circuitry configured to support a plurality of decompression schemes associated with more than one test generation tool, the decompression circuitry being connected between the input interface and the plurality of scan chains; and

configuration circuitry, responsive to a configuration stimulus, to configure the decompression circuitry to implement a selected decompression scheme from said plurality, wherein, on receipt of the compressed input test data from the input interface, the decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to said plurality of scan chains.

2. The data processing apparatus as claimed in claim 1, further comprising:

an output interface for outputting compressed output test data; and

compression circuitry configured to support a plurality of compression schemes associated with more than one test generation tool, the compression circuitry connected between the plurality of scan chains and the output interface;

the configuration circuitry further responsive to said configuration stimulus, to configure the compression circuitry to implement a selected compression scheme from said plurality, such that on receipt of the output test data from said plurality of scan chains, the compression circuitry applies the selected compression scheme to the output test data to produce said compressed output test data to be provided to said output interface.

3. The data processing apparatus as claimed in claim 1, wherein:

said decompression circuitry comprises a plurality of decompression blocks, each decompression block configured to implement one of the decompression schemes from said plurality of decompression schemes;

said configuration circuitry, responsive to the configuration stimulus, to select one of the decompression blocks, such that the decompression scheme associated with the selected decompression block is used to produce, from the compressed input test data, said input test data to be provided to said plurality of scan chains.

4. The data processing apparatus as claimed in claim 1, wherein:

said decompression circuitry is programmable, and said configuration stimulus provides programming data used by the configuration circuitry to configure the decompression circuitry to implement the selected decompression scheme.

5. The data processing apparatus as claimed in claim 2, wherein:

said compression circuitry comprises a plurality of compression blocks, each compression block configured to implement one of the compression schemes from said plurality of compression schemes;

said configuration circuitry, responsive to the configuration stimulus, to select one of the compression blocks, wherein the compression scheme implemented by the selected compression block is used to produce the compressed output test data from the output test data received by said plurality of scan chains.

6. The data processing apparatus as claimed in claim 2, wherein:

said compression circuitry is programmable, and said configuration stimulus provides programming data used by the configuration circuitry to configure the compression circuitry to implement the selected compression scheme.

7. The data processing apparatus as claimed in claim 1, further comprising:

a configuration interface configured to receive said configuration stimulus.

8. The data processing apparatus as claimed in claim 1, wherein said configuration stimulus is provided over the input interface that receives the compressed input test data.

9. The data processing apparatus as claimed in claim 8, wherein said configuration stimulus is provided within a header field accompanying the compressed input test data.

10. The data processing circuit as claimed in claim 1, wherein said plurality of scan chains comprises n scan chains, and said input interface comprises m input pins for receiving said compressed input test data, where n is greater than m.

11. The data processing circuit as claimed in claim 10, wherein said output interface comprises p output pins for outputting said compressed output test data, where n is greater than p.

12. The data processing apparatus as claimed in claim 11, wherein m equals p.

13. The data processing apparatus as claimed in claim 1, wherein the circuit block comprises processing circuitry for performing data processing operations.

14. The data processing apparatus as claimed in claim 1, wherein the circuit block comprises a memory circuit for storing data values.

15. An integrated circuit comprising:

a plurality of circuit blocks, at least one of said circuit blocks being a data processing circuit as claimed in claim 1; and

an interface for receiving said configuration stimulus;

whereby the decompression scheme employed in respect of said at least one of said circuit blocks is selectable having regard to the integrated circuit in which the at least one of said circuit blocks is incorporated.

16. The integrated circuit as claimed in claim 15, wherein said integrated circuit is a System-on-Chip (SoC).

17. A data processing apparatus comprising:

a circuit block to be tested;

a plurality of scan chains, each scan chain providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation;

an output interface for outputting compressed output test data;

compression circuitry configured to support a plurality of compression schemes associated with more than one test generation tool, the compression circuitry is connected between the plurality of scan chains and the output interface; and

configuration circuitry, responsive to a configuration stimulus, to configure the compression circuitry to implement a selected compression scheme from said plurality of compression schemes, wherein, on receipt of the output test data from said plurality of scan chains, the compression circuitry applies the selected compression scheme to the output test data to produce said compressed output test data for submission to said output interface.

18. A method of testing a circuit block within a data processing apparatus, comprising the steps of:

(a) providing a plurality of scan chains, each scan chain in said plurality providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block;

(b) receiving compressed input test data by decompression circuitry;

(c) responsive to a configuration stimulus, configuring said decompression circuitry to implement a selected decompression scheme from a plurality of decompression schemes associated with more than one test generation tool and supported by the decompression circuitry;

(d) on receipt by the decompression circuitry of the compressed input test data received at said step (b), applying the selected decompression scheme to the compressed input test data to produce the input test data; and

(e) providing to said plurality of scan chains the input test data produced at said step (d).

19. The method as claimed in claim 18, further comprising the steps of:

(f) responsive to said configuration stimulus, configuring said compression circuitry to implement a selected compression scheme from a plurality of compression schemes associated with more than one test generation tool and supported by said compression circuitry;

(g) on receipt by the compression circuitry of the output test data from said plurality of scan chains, applying the selected compression scheme to the output test data to produce compressed output test data; and

(h) providing to an output interface the compressed output test data produced at said step (g).

20. The method as claimed in claim 18, wherein:

at said step (b), the compressed input test data received is generated by a test generation tool; and

at said step (c), the configuration stimulus is chosen so as to configure the decompression circuitry to implement said selected decompression scheme having regard to at least one test generation algorithm employed by the test generation tool.

21. A data processing apparatus comprising:

circuit under test;

a plurality of scan chain means, each scan chain means comprising a means for providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit under test during a test mode of operation;

input interface means for receiving compressed input test data;

configurable decompression means for supporting a plurality of decompression schemes associated with more than one test generation tool, the configurable decompression means being connected between the input interface means and the plurality of scan chain means; and

configuration means, responsive to a configuration stimulus, for configuring the configurable decompression means to implement a selected decompression scheme from said plurality, such that on receipt of the compressed input test data from the input interface means the configurable decompression means applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to said plurality of scan chain means.